mb/google/drallion: Dynamicly disable memory channel
Disable memory channel by HW strap pin. Using for factory debug. BUG=b:139773082 BRANCH=N/A TEST=Rework HW strap pin and check /proc/mem_info Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ic5f53f0ba3bd432fbcb7513d2a8aa49d42f7a23e Reviewed-on: https://review.coreboot.org/c/coreboot/+/35241 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -286,4 +286,11 @@ void variant_mainboard_post_init_params(FSPM_UPD *mupd)
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FSP_M_CONFIG *fsp_m_cfg = &mupd->FspmConfig;
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if (fsp_m_cfg->PchIshEnable)
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fsp_m_cfg->PchIshEnable = is_ish_device_enabled();
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/*
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* Disable memory channel by HW strap pin, HW default is enable
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* 0: Enable both DIMMs, 3: Disable both DIMMs
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*/
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mupd->FspmConfig.DisableDimmChannel0 = gpio_get(DDR_CH0_EN) ? 0 : 3;
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mupd->FspmConfig.DisableDimmChannel1 = gpio_get(DDR_CH1_EN) ? 0 : 3;
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}
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@ -28,6 +28,10 @@
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/* Sensor detection pin */
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#define SENSOR_DET_360 GPP_H5
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/* DDR channel enable pin */
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#define DDR_CH0_EN GPP_F1
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#define DDR_CH1_EN GPP_F2
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/* Memory configuration board straps */
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#define GPIO_MEM_CONFIG_0 GPP_F12
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#define GPIO_MEM_CONFIG_1 GPP_F13
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