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mb/google/drallion: Dynamicly disable memory channel 

Disable memory channel by HW strap pin. Using for factory
debug.

BUG=b:139773082
BRANCH=N/A
TEST=Rework HW strap pin and check /proc/mem_info

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ic5f53f0ba3bd432fbcb7513d2a8aa49d42f7a23e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35241
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Eric Lai 2019-09-04 13:49:07 +08:00 committed by Patrick Georgi
parent cf9588040d
commit 0f47ff1be5
2 changed files with 11 additions and 0 deletions
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7
src/mainboard/google/drallion/variants/drallion/gpio.c
View File

@ -286,4 +286,11 @@ void variant_mainboard_post_init_params(FSPM_UPD *mupd)
FSP_M_CONFIG *fsp_m_cfg = &mupd->FspmConfig; FSP_M_CONFIG *fsp_m_cfg = &mupd->FspmConfig;
if (fsp_m_cfg->PchIshEnable) if (fsp_m_cfg->PchIshEnable)
fsp_m_cfg->PchIshEnable = is_ish_device_enabled(); fsp_m_cfg->PchIshEnable = is_ish_device_enabled();
/*
* Disable memory channel by HW strap pin, HW default is enable
* 0: Enable both DIMMs, 3: Disable both DIMMs
*/
mupd->FspmConfig.DisableDimmChannel0 = gpio_get(DDR_CH0_EN) ? 0 : 3;
mupd->FspmConfig.DisableDimmChannel1 = gpio_get(DDR_CH1_EN) ? 0 : 3;
} }

4
src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h
View File

@ -28,6 +28,10 @@
/* Sensor detection pin */ /* Sensor detection pin */
#define SENSOR_DET_360 GPP_H5 #define SENSOR_DET_360 GPP_H5
/* DDR channel enable pin */
#define DDR_CH0_EN GPP_F1
#define DDR_CH1_EN GPP_F2
/* Memory configuration board straps */ /* Memory configuration board straps */
#define GPIO_MEM_CONFIG_0 GPP_F12 #define GPIO_MEM_CONFIG_0 GPP_F12
#define GPIO_MEM_CONFIG_1 GPP_F13 #define GPIO_MEM_CONFIG_1 GPP_F13