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urara: Reduce MIPS PLL jitter 

The current MIPS PLL is configured in such a way that there is
excessive jitter.  Correct this by applying new PLL settings. The
resultant frequency is 546MHz instead of 550MHz.

BUG=chrome-os-partner:31438
TEST=tested on Pistachio bring up board as part of the JTAG
     loading script;
BRANCH=none

Change-Id: Ica1bfff29e01819b86cd2bb8b18d8adc9dfa3260
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 0c04354b49b73d234492521d81b6600d487175b0
Original-Change-Id: I28b41b1e82dbdf9da21bf0ab74f9722cdad923f1
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/245620
Original-Reviewed-by: James Hartley <james.hartley@imgtec.com>
Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: http://review.coreboot.org/9671
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Ionela Voinescu 2015-02-03 00:26:08 +00:00 committed by Patrick Georgi
parent a7023904e6
commit 0f58d0b941
1 changed files with 3 additions and 3 deletions
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6
src/mainboard/google/urara/bootblock.c
View File

@ -111,7 +111,7 @@ static int init_clocks(void)
/* The same frequency will be the input frequency for the SPFI block */
system_clk_setup(1);
/* MIPS CPU dividers: division by 1 -> 550 MHz
/* MIPS CPU dividers: division by 1 -> 546 MHz
* This is set up as we cannot make any assumption about
* the values set or not by the boot ROM code */
mips_clk_setup(0, 0);
@ -135,8 +135,8 @@ static int init_clocks(void)
ret = sys_pll_setup(2, 1);
if (ret != CLOCKS_OK)
return ret;
/* Setup MIPS PLL at 550 MHz */
ret = mips_pll_setup(2, 1, 13, 275);
/* Setup MIPS PLL at 546 MHz */
ret = mips_pll_setup(2, 1, 1, 21);
if (ret != CLOCKS_OK)
return ret;
return CLOCKS_OK;