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AGESA: Drop CAR teardown without POSTCAR_STAGE 

Except for family15, all AGESA boards have moved
away from AGESA_LEGACY_WRAPPER, thus they all
have POSTCAR_STAGE now.

AGESA family15 boards remain at AGESA_LEGACY=y, but
those boards have per-board romstage.c files and
are not touched here.

Change-Id: If750766cc7a9ecca4641a8f14e1ab15e9abb7ff5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2017-09-07 06:46:46 +03:00
parent 63fac81fc8
commit 0f6c0b1a6f
5 changed files with 29 additions and 144 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

68
src/cpu/amd/agesa/romstage.c
View File

@ -31,6 +31,12 @@
#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
#error "Only EARLY_CBMEM_INIT is supported."
#endif
#if !IS_ENABLED(CONFIG_POSTCAR_STAGE)
#error "Only POSTCAR_STAGE is supported."
#endif
#if HAS_LEGACY_WRAPPER
#error "LEGACY_WRAPPER code not supported"
#endif
void asmlinkage early_all_cores(void)
{
@ -47,8 +53,7 @@ static void fill_sysinfo(struct sysinfo *cb)
memset(cb, 0, sizeof(*cb));
cb->s3resume = acpi_is_wakeup_s3();
if (!HAS_LEGACY_WRAPPER)
agesa_set_interface(cb);
agesa_set_interface(cb);
}
void * asmlinkage romstage_main(unsigned long bist)
@ -77,31 +82,25 @@ void * asmlinkage romstage_main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
if (!HAS_LEGACY_WRAPPER) {
agesa_execute_state(cb, AMD_INIT_RESET);
agesa_execute_state(cb, AMD_INIT_RESET);
agesa_execute_state(cb, AMD_INIT_EARLY);
agesa_execute_state(cb, AMD_INIT_EARLY);
timestamp_add_now(TS_BEFORE_INITRAM);
timestamp_add_now(TS_BEFORE_INITRAM);
if (!cb->s3resume)
agesa_execute_state(cb, AMD_INIT_POST);
else
agesa_execute_state(cb, AMD_INIT_RESUME);
if (!cb->s3resume)
agesa_execute_state(cb, AMD_INIT_POST);
else
agesa_execute_state(cb, AMD_INIT_RESUME);
/* FIXME: Detect if TSC frequency changed during raminit? */
timestamp_rescale_table(1, 4);
timestamp_add_now(TS_AFTER_INITRAM);
/* FIXME: Detect if TSC frequency changed during raminit? */
timestamp_rescale_table(1, 4);
timestamp_add_now(TS_AFTER_INITRAM);
} else {
agesa_main(cb);
}
if (IS_ENABLED(CONFIG_POSTCAR_STAGE))
fixup_cbmem_to_UC(cb->s3resume);
/* Work around AGESA setting all memory as WB on normal
* boot path.
*/
fixup_cbmem_to_UC(cb->s3resume);
cbmem_initted = !cbmem_recovery(cb->s3resume);
@ -112,14 +111,6 @@ void * asmlinkage romstage_main(unsigned long bist)
romstage_handoff_init(cb->s3resume);
if (!IS_ENABLED(CONFIG_POSTCAR_STAGE)) {
uintptr_t stack_top = romstage_ram_stack_base(
HIGH_ROMSTAGE_STACK_SIZE, ROMSTAGE_STACK_CBMEM);
stack_top += HIGH_ROMSTAGE_STACK_SIZE;
printk(BIOS_DEBUG, "Move CAR stack.\n");
return (void*)stack_top;
}
postcar_frame_init(&pcf, HIGH_ROMSTAGE_STACK_SIZE);
recover_postcar_frame(&pcf, cb->s3resume);
@ -127,20 +118,3 @@ void * asmlinkage romstage_main(unsigned long bist)
/* We do not return. */
return NULL;
}
#if !IS_ENABLED(CONFIG_POSTCAR_STAGE)
void asmlinkage romstage_after_car(void)
{
struct sysinfo romstage_state;
struct sysinfo *cb = &romstage_state;
printk(BIOS_DEBUG, "CAR disabled.\n");
fill_sysinfo(cb);
if (HAS_LEGACY_WRAPPER)
agesa_postcar(cb);
run_ramstage();
}
#endif

20
src/vendorcode/amd/agesa/f12/gcccar.inc
View File

@ -611,13 +611,6 @@ fam12_enable_stack_hook_exit:
* Return any family specific controls to their 'standard'
* settings for using cache with main memory.
*
* Note: Customized for coreboot:
* A wbinvd is used to send cache to memory. The existing stack is preserved
* at its original location and additional information is preserved (e.g.
* coreboot CAR globals, heap structures, etc.). This implementation should
* NOT be used with S3 resume IF the stack/cache area is not reserved and
* over system memory.
*
* Inputs:
* ESI - [31:24] flags; [15,8]= Node#; [7,0]= core#
* Outputs:
@ -672,18 +665,7 @@ fam12_enable_stack_hook_exit:
mov %ax, %bx # Save INVD -> WBINVD bit
btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion
_WRMSR
#--------------------------------------------------------------------------
# Send cache to memory. Preserve stack and coreboot CAR globals.
# This shouldn't be used with S3 resume IF the stack/cache area is
# not reserved and over system memory.
#--------------------------------------------------------------------------
#if !IS_ENABLED(CONFIG_POSTCAR_STAGE)
wbinvd
#else
invd
#endif
invd # Clear the cache tag RAMs
mov %bx, %ax # Restore INVD -> WBINVD bit
_WRMSR

20
src/vendorcode/amd/agesa/f14/gcccar.inc
View File

@ -770,13 +770,6 @@ fam14_enable_stack_hook_exit:
* Return any family specific controls to their 'standard'
* settings for using cache with main memory.
*
* Note: Customized for coreboot:
* A wbinvd is used to send cache to memory. The existing stack is preserved
* at its original location and additional information is preserved (e.g.
* coreboot CAR globals, heap structures, etc.). This implementation should
* NOT be used with S3 resume IF the stack/cache area is not reserved and
* over system memory.
*
* Inputs:
* ESI - [31:24] flags; [15,8]= Node#; [7,0]= core#
* Outputs:
@ -820,18 +813,7 @@ fam14_enable_stack_hook_exit:
_RDMSR
btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion
_WRMSR
#--------------------------------------------------------------------------
# Send cache to memory. Preserve stack and coreboot CAR globals.
# This shouldn't be used with S3 resume IF the stack/cache area is
# not reserved and over system memory.
#--------------------------------------------------------------------------
#if !IS_ENABLED(CONFIG_POSTCAR_STAGE)
wbinvd
#else
invd
#endif
invd # Clear the cache tag RAMs
bts $INVD_WBINVD, %eax # Turn on Conversion of INVD to WBINVD
_WRMSR

33
src/vendorcode/amd/agesa/f15tn/gcccar.inc
View File

@ -1033,13 +1033,6 @@ fam15_enable_stack_hook_exit:
* Return any family specific controls to their 'standard'
* settings for using cache with main memory.
*
* Note: Customized for coreboot:
* A wbinvd is used to send cache to memory. The existing stack is preserved
* at its original location and additional information is preserved (e.g.
* coreboot CAR globals, heap structures, etc.). This implementation should
* NOT be used with S3 resume IF the stack/cache area is not reserved and
* over system memory.
*
* Inputs:
* ESI - [31:24] flags; [15,8]= Node#; [7,0]= core#
* Outputs:
@ -1257,18 +1250,7 @@ fam15_disable_stack_remote_read_exit:
_RDMSR
btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion
_WRMSR
#--------------------------------------------------------------------------
# Send cache to memory. Preserve stack and coreboot CAR globals.
# This shouldn't be used with S3 resume IF the stack/cache area is
# not reserved and over system memory.
#--------------------------------------------------------------------------
#if !IS_ENABLED(CONFIG_POSTCAR_STAGE)
wbinvd
#else
invd
#endif
invd # Clear the cache tag RAMs
#.if (bh == 01h) || (bh == 03h) ; Is this TN or KM?
cmp $01, %bh
jz 4f
@ -1901,17 +1883,8 @@ ClearTheStack: # Stack base is in SS, stack pointer is
.endm
/*****************************************************************************
* AMD_DISABLE_STACK: Implementation is modified for coreboot from
* the original AMD intent. A WBINVD is used in the HOOK
* to send dirty cache contents to DRAM backing before
* disabling cache-as-ram. This is not safe for S3 resume.
*
* todo:
* * rework PI/AGESA source to set DRAM to UC to send
* writes directly to memory
* * move DCACHE_BASE or use postcar stage for teardown
* to eliminate car_migrated problem that will occur
* after wbinvd is changed back to invd
* AMD_DISABLE_STACK: Destroy the stack inside the cache. This routine
* should only be executed on the BSP
*
* In:
* none

32
src/vendorcode/amd/agesa/f16kb/gcccar.inc
View File

@ -269,13 +269,6 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))
* Read family specific values to determine the node and core
* numbers for the core executing this code.
*
* Note: Customized for coreboot:
* A wbinvd is used to send cache to memory. The existing stack is preserved
* at its original location and additional information is preserved (e.g.
* coreboot CAR globals, heap structures, etc.). This implementation should
* NOT be used with S3 resume IF the stack/cache area is not reserved and
* over system memory.
*
* Inputs:
* none
* Outputs:
@ -609,17 +602,7 @@ fam16_disable_stack_remote_read_exit:
_RDMSR
btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion
_WRMSR
#--------------------------------------------------------------------------
# Send cache to memory. Preserve stack and coreboot CAR globals.
# This shouldn't be used with S3 resume IF the stack/cache area is
# not reserved and over system memory.
#--------------------------------------------------------------------------
#if !IS_ENABLED(CONFIG_POSTCAR_STAGE)
wbinvd
#else
invd
#endif
invd # Clear the cache tag RAMs
#Do Standard Family 16 work
mov $HWCR, %ecx # MSR:C001_0015h
@ -1264,17 +1247,8 @@ ClearTheStack: # Stack base is in SS, stack pointer is
.endm
/*****************************************************************************
* AMD_DISABLE_STACK: Implementation is modified for coreboot from
* the original AMD intent. A WBINVD is used in the HOOK
* to send dirty cache contents to DRAM backing before
* disabling cache-as-ram. This is not safe for S3 resume.
*
* todo:
* * rework PI/AGESA source to set DRAM to UC to send
* writes directly to memory
* * move DCACHE_BASE or use postcar stage for teardown
* to eliminate car_migrated problem that will occur
* after wbinvd is changed back to invd
* AMD_DISABLE_STACK: Destroy the stack inside the cache. This routine
* should only be executed on the BSP
*
* In:
* none