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soc/intel/denverton_ns: Add the Primary to Sideband Bridge definition 

This change adds the Primary to Sideband Bridge(B0, D31, F1)
definition for the platform in order to maintain the common block
API build.

BUG=b:213574324
TEST=Build platforms coreboot images successfully.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I1c4ddfce6cc6e41b2c63f99990d105b4bbb6f175
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
John Zhao 2022-01-13 09:09:05 -08:00 committed by Subrata Banik
parent ac24a96579
commit 0f76a18c3a
1 changed files with 1 additions and 0 deletions
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1
src/soc/intel/denverton_ns/include/soc/pci_devs.h
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@ -143,6 +143,7 @@
#define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5)
#define PCH_DEV_LPC _PCH_DEV(LPC, 0)
#define PCH_DEV_SPI _PCH_DEV(LPC, 5)
#define PCH_DEV_P2SB _PCH_DEV(LPC, 1)
#define PCH_DEV_SMBUS _PCH_DEV(LPC, 4)
/* VT-d support value to match FSP settings */