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mb/google/dedede/var/boten: Set the xHCI LFPS period sampling off time to 0ms 

LTE module L850-GL may encounter U3 wakeup race condition with the host.
Setting xHCI LFPS periodic sampling off time to 0ms so that the host would not
miss the device-initiated U3 wakeup thus avoid the race condition.

BUG=b:187801363
BRANCH=dedede
TEST=flash the image to the device. Run following command to check the bits[7:4] is 0x0:
iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"

Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I9328e758ed92389e44b25ff4daf6ec19b37ae7d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Ben Kao <ben.kao@intel.corp-partner.google.com>
This commit is contained in:
stanley.wu 2021-07-29 17:50:36 +08:00 committed by Patrick Georgi
parent f80e6d6f56
commit 0f80767ee1
1 changed files with 3 additions and 0 deletions
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src/mainboard/google/dedede/variants/boten/overridetree.cb
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@ -80,6 +80,9 @@ chip soc/intel/jasperlake
register "SlowSlewRate" = "SlewRateFastBy8" register "SlowSlewRate" = "SlewRateFastBy8"
register "FastPkgCRampDisable" = "1" register "FastPkgCRampDisable" = "1"
# Set xHCI LFPS period sampling off time to 0 ms
register "xhci_lfps_sampling_offtime_ms" = "0"
device domain 0 on device domain 0 on
device pci 04.0 on device pci 04.0 on
chip drivers/intel/dptf chip drivers/intel/dptf