From 0f82905be42f0ad955af0f48394541f35f6fd85b Mon Sep 17 00:00:00 2001
From: David Wu <david_wu@quantatw.com>
Date: Mon, 11 Dec 2017 14:08:11 +0800
Subject: [PATCH] mb/google/fizz: Enable SATA on port 0

Enable SATA port 0 to support SATA HDD.

BUG=b:69950854
BRANCH=None
TEST=emerge-fizz coreboot and boot on fizz dut

Change-Id: Ifbf5950151758286f8bff7250a68d9d0b3975ef9
Signed-off-by: David Wu <david_wu@quantatw.com>
Reviewed-on: https://review.coreboot.org/22815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/mainboard/google/fizz/devicetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb
index 55d59fe96a..d0449d9736 100644
--- a/src/mainboard/google/fizz/devicetree.cb
+++ b/src/mainboard/google/fizz/devicetree.cb
@@ -56,6 +56,7 @@ chip soc/intel/skylake
 	register "EnableSata" = "1"
 	register "SataSalpSupport" = "1"
 	register "SataMode" = "1"
+	register "SataPortsEnable[0]" = "1"
 	register "SataPortsEnable[1]" = "1"
 	register "SataPortsDevSlp[1]" = "1"
 	register "EnableAzalia" = "1"