soc/intel/skylake: drop support for FSP 1.1
This drops support for FSP 1.1 in soc/intel/skylake, after all boards have been migrated to FSP 2.0, which is backwards compatible. Any moving of files happens in a follow-up commit to make review easier. Change-Id: I0dd2eab0edfda0545ff94c3908b8574d5ad830bd Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35813 Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michael Niewöhner
Nico Huber
parent
a9e07f9444
commit
0f91f79447
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@ -17,7 +17,6 @@ config BOARD_GOOGLE_BASEBOARD_GLADOS
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_LPC_TPM
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select MAINBOARD_HAS_TPM1
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select MAINBOARD_USES_FSP2_0
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select SOC_INTEL_SKYLAKE
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select SYSTEM_TYPE_LAPTOP
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@ -19,7 +19,6 @@ config BOARD_SPECIFIC_OPTIONS
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_LPC_TPM
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select SOC_INTEL_SKYLAKE
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select MAINBOARD_USES_FSP2_0
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config VBOOT
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select EC_GOOGLE_CHROMEEC_SWITCHES
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@ -31,7 +31,6 @@ config BOARD_SPECIFIC_OPTIONS
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select HAVE_CMOS_DEFAULT
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select MAINBOARD_USES_IFD_GBE_REGION
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select USE_INTEL_FSP_MP_INIT
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select MAINBOARD_USES_FSP2_0
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config IRQ_SLOT_COUNT
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int
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@ -7,7 +7,6 @@ config BOARD_PURISM_BASEBOARD_LIBREM_SKL
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select INTEL_LPSS_UART_FOR_CONSOLE
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select SOC_INTEL_COMMON_BLOCK_HDA_VERB
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select SOC_INTEL_SKYLAKE
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select MAINBOARD_USES_FSP2_0
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select SPD_READ_BY_WORD
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select MAINBOARD_HAS_LPC_TPM
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@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS
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select SUPERIO_ITE_IT8528E
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select SOC_INTEL_KABYLAKE
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select SOC_INTEL_COMMON_BLOCK_HDA_VERB
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select MAINBOARD_USES_FSP2_0
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select MAINBOARD_HAS_LPC_TPM
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select MAINBOARD_HAS_TPM2
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select MAINBOARD_HAS_LIBGFXINIT
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@ -10,7 +10,6 @@ config SOC_INTEL_SKYLAKE
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config SOC_INTEL_KABYLAKE
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bool
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select SOC_INTEL_COMMON_SKYLAKE_BASE
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select MAINBOARD_USES_FSP2_0
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help
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Intel Kabylake support
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@ -33,7 +32,7 @@ config CPU_SPECIFIC_OPTIONS
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select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
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select CPU_INTEL_COMMON_HYPERTHREADING
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select C_ENVIRONMENT_BOOTBLOCK
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select FSP_M_XIP if MAINBOARD_USES_FSP2_0
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select FSP_M_XIP
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select FSP_T_XIP if FSP_CAR
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select GENERIC_GPIO_LIB
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select HAVE_FSP_GOP
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@ -41,12 +40,14 @@ config CPU_SPECIFIC_OPTIONS
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select HAVE_SMI_HANDLER
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select INTEL_CAR_NEM_ENHANCED
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select INTEL_GMA_ACPI
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select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
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select IOAPIC
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select MRC_SETTINGS_PROTECT
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select NO_FIXED_XIP_ROM_SIZE
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select PARALLEL_MP
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select PARALLEL_MP_AP_WORK
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select PCIEX_LENGTH_64MB
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select PLATFORM_USES_FSP2_0
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select REG_SCRIPT
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select SA_ENABLE_DPR
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select SMP
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@ -78,34 +79,16 @@ config CPU_SPECIFIC_OPTIONS
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select TSC_MONOTONIC_TIMER
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select TSC_SYNC_MFENCE
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select UDELAY_TSC
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select UDK_2015_BINDING
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config FSP_HYPERTHREADING
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bool "Enable Hyper-Threading"
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depends on MAINBOARD_USES_FSP2_0
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default y
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config CPU_INTEL_NUM_FIT_ENTRIES
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int
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default 10
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config MAINBOARD_USES_FSP2_0
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bool
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default n
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config USE_FSP2_0_DRIVER
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def_bool y
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depends on MAINBOARD_USES_FSP2_0
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select PLATFORM_USES_FSP2_0
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select UDK_2015_BINDING
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select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
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config USE_FSP1_1_DRIVER
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def_bool y
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depends on !MAINBOARD_USES_FSP2_0
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select PLATFORM_USES_FSP1_1
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select DISPLAY_FSP_ENTRY_POINTS
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select SKIP_FSP_CAR
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config CHROMEOS
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select CHROMEOS_RAMOOPS_DYNAMIC
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@ -243,17 +226,14 @@ config NHLT_DA7219
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config FSP_HEADER_PATH
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string "Location of FSP headers"
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depends on MAINBOARD_USES_FSP2_0
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# Use KabylakeFsp for both Skylake and Kabylake as it supports both.
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# SkylakeFsp is FSP 1.1 and therefore incompatible.
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default "3rdparty/fsp/KabylakeFspBinPkg/Include/" if SOC_INTEL_SKYLAKE
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default "3rdparty/fsp/KabylakeFspBinPkg/Include/" if SOC_INTEL_KABYLAKE
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default "3rdparty/fsp/KabylakeFspBinPkg/Include/"
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config FSP_FD_PATH
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string
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depends on FSP_USE_REPO
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default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" if SOC_INTEL_SKYLAKE
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default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" if SOC_INTEL_KABYLAKE
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default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd"
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config SPI_FLASH_INCLUDE_ALL_DRIVERS
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bool
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@ -261,8 +241,7 @@ config SPI_FLASH_INCLUDE_ALL_DRIVERS
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config MAX_ROOT_PORTS
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int
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default 24 if PLATFORM_USES_FSP2_0
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default 20 if PLATFORM_USES_FSP1_1
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default 24
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config NO_FADT_8042
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bool
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@ -37,13 +37,12 @@ romstage-y += memmap.c
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romstage-y += me.c
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romstage-y += pmc.c
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romstage-y += pmutil.c
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romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
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romstage-y += reset.c
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romstage-y += spi.c
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romstage-y += uart.c
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
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ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += chip.c
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ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += chip_fsp20.c
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ramstage-y += chip_fsp20.c
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ramstage-y += cpu.c
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ramstage-y += elog.c
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ramstage-y += finalize.c
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@ -59,7 +58,7 @@ ramstage-y += memmap.c
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ramstage-y += p2sb.c
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ramstage-y += pmc.c
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ramstage-y += pmutil.c
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ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
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ramstage-y += reset.c
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ramstage-y += sd.c
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ramstage-y += smmrelocate.c
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ramstage-y += spi.c
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@ -101,13 +100,7 @@ endif
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CPPFLAGS_common += -I$(src)/soc/intel/skylake
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CPPFLAGS_common += -I$(src)/soc/intel/skylake/include
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ifeq ($(CONFIG_PLATFORM_USES_FSP1_1),y)
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CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp11
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CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/skylake
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else
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CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp20
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endif
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# Currently used for microcode path.
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CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARDDIR)
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@ -38,10 +38,6 @@ void bootblock_soc_early_init(void)
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void bootblock_soc_init(void)
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{
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/* FSP 2.0 does not provide FSP-T/TempRamInit init support yet */
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if (CONFIG(PLATFORM_USES_FSP1_1))
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bootblock_fsp_temp_ram_init();
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/*
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* Perform early chipset initialization before fsp memory init
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* example: pirq->irq programming, enabling smbus, set pmcbase
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@ -1,861 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015-2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/acpi.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <fsp/util.h>
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#include <intelblocks/cfg.h>
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#include <intelblocks/itss.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/xdci.h>
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#include <intelpch/lockdown.h>
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#include <soc/acpi.h>
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#include <soc/interrupt.h>
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#include <soc/irq.h>
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#include <soc/itss.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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#include <string.h>
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#include "chip.h"
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void soc_init_pre_device(void *chip_info)
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{
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/* Snapshot the current GPIO IRQ polarities. FSP is setting a
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* default policy that doesn't honor boards' requirements. */
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itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
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/* Perform silicon specific init. */
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intel_silicon_init();
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/* Restore GPIO IRQ polarities back to previous settings. */
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itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
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}
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void soc_fsp_load(void)
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{
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fsp_load();
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}
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static void pci_domain_set_resources(struct device *dev)
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{
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assign_resources(dev->link_list);
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}
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static struct device_operations pci_domain_ops = {
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.read_resources = &pci_domain_read_resources,
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.set_resources = &pci_domain_set_resources,
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.scan_bus = &pci_domain_scan_bus,
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#if CONFIG(HAVE_ACPI_TABLES)
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.write_acpi_tables = &northbridge_write_acpi_tables,
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.acpi_name = &soc_acpi_name,
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#endif
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};
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static struct device_operations cpu_bus_ops = {
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.init = DEVICE_NOOP,
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#if CONFIG(HAVE_ACPI_TABLES)
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.acpi_fill_ssdt_generator = generate_cpu_entries,
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#endif
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};
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static void soc_enable(struct device *dev)
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{
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/* Set the operations if it is a special bus type */
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if (dev->path.type == DEVICE_PATH_DOMAIN)
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dev->ops = &pci_domain_ops;
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else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
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dev->ops = &cpu_bus_ops;
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}
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struct chip_operations soc_intel_skylake_ops = {
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CHIP_NAME("Intel Skylake")
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.enable_dev = &soc_enable,
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.init = &soc_init_pre_device,
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};
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/* UPD parameters to be initialized before SiliconInit */
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void soc_silicon_init_params(SILICON_INIT_UPD *params)
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{
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struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC);
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const struct soc_intel_skylake_config *config = config_of(dev);
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int i;
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memcpy(params->SerialIoDevMode, config->SerialIoDevMode,
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sizeof(params->SerialIoDevMode));
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for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
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params->PortUsb20Enable[i] =
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config->usb2_ports[i].enable;
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params->Usb2OverCurrentPin[i] =
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config->usb2_ports[i].ocpin;
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params->Usb2AfePetxiset[i] =
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config->usb2_ports[i].pre_emp_bias;
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params->Usb2AfeTxiset[i] =
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config->usb2_ports[i].tx_bias;
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params->Usb2AfePredeemp[i] =
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config->usb2_ports[i].tx_emp_enable;
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params->Usb2AfePehalfbit[i] =
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config->usb2_ports[i].pre_emp_bit;
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}
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for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
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params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
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params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
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if (config->usb3_ports[i].tx_de_emp) {
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params->Usb3HsioTxDeEmphEnable[i] = 1;
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params->Usb3HsioTxDeEmph[i] =
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config->usb3_ports[i].tx_de_emp;
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}
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if (config->usb3_ports[i].tx_downscale_amp) {
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params->Usb3HsioTxDownscaleAmpEnable[i] = 1;
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params->Usb3HsioTxDownscaleAmp[i] =
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config->usb3_ports[i].tx_downscale_amp;
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}
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}
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memcpy(params->PcieRpEnable, config->PcieRpEnable,
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sizeof(params->PcieRpEnable));
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memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport,
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sizeof(params->PcieRpClkReqSupport));
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memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber,
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sizeof(params->PcieRpClkReqNumber));
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memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug,
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sizeof(params->PcieRpHotPlug));
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params->EnableLan = config->EnableLan;
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params->Cio2Enable = config->Cio2Enable;
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params->SataSalpSupport = config->SataSalpSupport;
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memcpy(params->SataPortsEnable, config->SataPortsEnable,
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sizeof(params->SataPortsEnable));
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memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
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sizeof(params->SataPortsDevSlp));
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params->SsicPortEnable = config->SsicPortEnable;
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params->SmbusEnable = config->SmbusEnable;
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params->ScsEmmcEnabled = config->ScsEmmcEnabled;
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params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
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params->ScsSdCardEnabled = config->ScsSdCardEnabled;
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/* Enable ISH if device is on */
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dev = pcidev_path_on_root(PCH_DEVFN_ISH);
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params->IshEnable = dev ? dev->enabled : 0;
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params->EnableAzalia = config->EnableAzalia;
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params->IoBufferOwnership = config->IoBufferOwnership;
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params->DspEnable = config->DspEnable;
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params->Device4Enable = config->Device4Enable;
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params->EnableSata = config->EnableSata;
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params->SataMode = config->SataMode;
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params->LockDownConfigGlobalSmi = config->LockDownConfigGlobalSmi;
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params->LockDownConfigRtcLock = config->LockDownConfigRtcLock;
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if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) {
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params->LockDownConfigBiosInterface = 0;
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params->LockDownConfigBiosLock = 0;
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params->LockDownConfigSpiEiss = 0;
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}
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/* only replacing preexisting subsys ID defaults when non-zero */
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if (CONFIG_SUBSYSTEM_VENDOR_ID != 0)
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params->PchConfigSubSystemVendorId = CONFIG_SUBSYSTEM_VENDOR_ID;
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if (CONFIG_SUBSYSTEM_DEVICE_ID != 0)
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params->PchConfigSubSystemId = CONFIG_SUBSYSTEM_DEVICE_ID;
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params->WakeConfigWolEnableOverride =
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config->WakeConfigWolEnableOverride;
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params->WakeConfigPcieWakeFromDeepSx =
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config->WakeConfigPcieWakeFromDeepSx;
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params->PmConfigDeepSxPol = config->PmConfigDeepSxPol;
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params->PmConfigSlpS3MinAssert = config->PmConfigSlpS3MinAssert;
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params->PmConfigSlpS4MinAssert = config->PmConfigSlpS4MinAssert;
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params->PmConfigSlpSusMinAssert = config->PmConfigSlpSusMinAssert;
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params->PmConfigSlpAMinAssert = config->PmConfigSlpAMinAssert;
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params->PmConfigPciClockRun = config->PmConfigPciClockRun;
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params->PmConfigSlpStrchSusUp = config->PmConfigSlpStrchSusUp;
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params->PmConfigPwrBtnOverridePeriod =
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config->PmConfigPwrBtnOverridePeriod;
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params->PmConfigPwrCycDur = config->PmConfigPwrCycDur;
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params->SerialIrqConfigSirqEnable = config->serirq_mode != SERIRQ_OFF;
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params->SerialIrqConfigSirqMode =
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config->serirq_mode == SERIRQ_CONTINUOUS;
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params->SerialIrqConfigStartFramePulse =
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config->SerialIrqConfigStartFramePulse;
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params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
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for (i = 0; i < ARRAY_SIZE(config->i2c_voltage); i++)
|
||||
params->SerialIoI2cVoltage[i] = config->i2c_voltage[i];
|
||||
|
||||
/*
|
||||
* To disable Heci, the Psf needs to be left unlocked
|
||||
* by FSP after end of post sequence. Based on the devicetree
|
||||
* setting, we set the appropriate PsfUnlock policy in Fsp,
|
||||
* do the changes and then lock it back in coreboot
|
||||
*
|
||||
*/
|
||||
params->PsfUnlock = !config->HeciEnabled;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++)
|
||||
fill_vr_domain_config(params, i, &config->domain_vr_config[i]);
|
||||
|
||||
/* Show SPI controller if enabled in devicetree.cb */
|
||||
dev = pcidev_path_on_root(PCH_DEVFN_SPI);
|
||||
params->ShowSpiController = dev ? dev->enabled : 0;
|
||||
|
||||
/* Enable xDCI controller if enabled in devicetree and allowed */
|
||||
dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
|
||||
if (dev) {
|
||||
if (!xdci_can_enable())
|
||||
dev->enabled = 0;
|
||||
params->XdciEnable = dev->enabled;
|
||||
} else {
|
||||
params->XdciEnable = 0;
|
||||
}
|
||||
|
||||
params->SendVrMbxCmd = config->SendVrMbxCmd;
|
||||
|
||||
/* Acoustic Noise Mitigation */
|
||||
params->AcousticNoiseMitigation = config->AcousticNoiseMitigation;
|
||||
params->SlowSlewRateForIa = config->SlowSlewRateForIa;
|
||||
params->SlowSlewRateForGt = config->SlowSlewRateForGt;
|
||||
params->SlowSlewRateForSa = config->SlowSlewRateForSa;
|
||||
params->FastPkgCRampDisable = config->FastPkgCRampDisable;
|
||||
|
||||
/* Legacy 8254 timer support */
|
||||
params->Early8254ClockGatingEnable = !CONFIG_USE_LEGACY_8254_TIMER;
|
||||
|
||||
soc_irq_settings(params);
|
||||
}
|
||||
|
||||
void soc_display_silicon_init_params(const SILICON_INIT_UPD *original,
|
||||
SILICON_INIT_UPD *params)
|
||||
{
|
||||
/* Display the parameters for SiliconInit */
|
||||
printk(BIOS_SPEW, "UPD values for SiliconInit:\n");
|
||||
fsp_display_upd_value("LogoPtr", 4,
|
||||
(uint32_t)original->LogoPtr,
|
||||
(uint32_t)params->LogoPtr);
|
||||
fsp_display_upd_value("LogoSize", 4,
|
||||
(uint32_t)original->LogoSize,
|
||||
(uint32_t)params->LogoSize);
|
||||
fsp_display_upd_value("GraphicsConfigPtr", 4,
|
||||
(uint32_t)original->GraphicsConfigPtr,
|
||||
(uint32_t)params->GraphicsConfigPtr);
|
||||
fsp_display_upd_value("MicrocodeRegionBase", 4,
|
||||
(uint32_t)original->MicrocodeRegionBase,
|
||||
(uint32_t)params->MicrocodeRegionBase);
|
||||
fsp_display_upd_value("MicrocodeRegionSize", 4,
|
||||
(uint32_t)original->MicrocodeRegionSize,
|
||||
(uint32_t)params->MicrocodeRegionSize);
|
||||
fsp_display_upd_value("TurboMode", 1,
|
||||
(uint32_t)original->TurboMode,
|
||||
(uint32_t)params->TurboMode);
|
||||
fsp_display_upd_value("Device4Enable", 1,
|
||||
original->Device4Enable,
|
||||
params->Device4Enable);
|
||||
fsp_display_upd_value("PcieRpEnable[0]", 1, original->PcieRpEnable[0],
|
||||
params->PcieRpEnable[0]);
|
||||
fsp_display_upd_value("PcieRpEnable[1]", 1, original->PcieRpEnable[1],
|
||||
params->PcieRpEnable[1]);
|
||||
fsp_display_upd_value("PcieRpEnable[2]", 1, original->PcieRpEnable[2],
|
||||
params->PcieRpEnable[2]);
|
||||
fsp_display_upd_value("PcieRpEnable[3]", 1, original->PcieRpEnable[3],
|
||||
params->PcieRpEnable[3]);
|
||||
fsp_display_upd_value("PcieRpEnable[4]", 1, original->PcieRpEnable[4],
|
||||
params->PcieRpEnable[4]);
|
||||
fsp_display_upd_value("PcieRpEnable[5]", 1, original->PcieRpEnable[5],
|
||||
params->PcieRpEnable[5]);
|
||||
fsp_display_upd_value("PcieRpEnable[6]", 1, original->PcieRpEnable[6],
|
||||
params->PcieRpEnable[6]);
|
||||
fsp_display_upd_value("PcieRpEnable[7]", 1, original->PcieRpEnable[7],
|
||||
params->PcieRpEnable[7]);
|
||||
fsp_display_upd_value("PcieRpEnable[8]", 1, original->PcieRpEnable[8],
|
||||
params->PcieRpEnable[8]);
|
||||
fsp_display_upd_value("PcieRpEnable[9]", 1, original->PcieRpEnable[9],
|
||||
params->PcieRpEnable[9]);
|
||||
fsp_display_upd_value("PcieRpEnable[10]", 1, original->PcieRpEnable[10],
|
||||
params->PcieRpEnable[10]);
|
||||
fsp_display_upd_value("PcieRpEnable[11]", 1, original->PcieRpEnable[11],
|
||||
params->PcieRpEnable[11]);
|
||||
fsp_display_upd_value("PcieRpEnable[12]", 1, original->PcieRpEnable[12],
|
||||
params->PcieRpEnable[12]);
|
||||
fsp_display_upd_value("PcieRpEnable[13]", 1, original->PcieRpEnable[13],
|
||||
params->PcieRpEnable[13]);
|
||||
fsp_display_upd_value("PcieRpEnable[14]", 1, original->PcieRpEnable[14],
|
||||
params->PcieRpEnable[14]);
|
||||
fsp_display_upd_value("PcieRpEnable[15]", 1, original->PcieRpEnable[15],
|
||||
params->PcieRpEnable[15]);
|
||||
fsp_display_upd_value("PcieRpEnable[16]", 1, original->PcieRpEnable[16],
|
||||
params->PcieRpEnable[16]);
|
||||
fsp_display_upd_value("PcieRpEnable[17]", 1, original->PcieRpEnable[17],
|
||||
params->PcieRpEnable[17]);
|
||||
fsp_display_upd_value("PcieRpEnable[18]", 1, original->PcieRpEnable[18],
|
||||
params->PcieRpEnable[18]);
|
||||
fsp_display_upd_value("PcieRpEnable[19]", 1, original->PcieRpEnable[19],
|
||||
params->PcieRpEnable[19]);
|
||||
fsp_display_upd_value("PcieRpClkReqSupport[0]", 1,
|
||||
original->PcieRpClkReqSupport[0],
|
||||
params->PcieRpClkReqSupport[0]);
|
||||
fsp_display_upd_value("PcieRpClkReqSupport[1]", 1,
|
||||
original->PcieRpClkReqSupport[1],
|
||||
params->PcieRpClkReqSupport[1]);
|
||||
fsp_display_upd_value("PcieRpClkReqSupport[2]", 1,
|
||||
original->PcieRpClkReqSupport[2],
|
||||
params->PcieRpClkReqSupport[2]);
|
||||
fsp_display_upd_value("PcieRpClkReqSupport[3]", 1,
|
||||
original->PcieRpClkReqSupport[3],
|
||||
params->PcieRpClkReqSupport[3]);
|
||||
fsp_display_upd_value("PcieRpClkReqSupport[4]", 1,
|
||||
original->PcieRpClkReqSupport[4],
|
||||
params->PcieRpClkReqSupport[4]);
|
||||
fsp_display_upd_value("PcieRpClkReqSupport[5]", 1,
|
||||
original->PcieRpClkReqSupport[5],
|
||||
params->PcieRpClkReqSupport[5]);
|
||||
fsp_display_upd_value("PcieRpClkReqSupport[6]", 1,
|
||||
original->PcieRpClkReqSupport[6],
|
||||
params->PcieRpClkReqSupport[6]);
|
||||
fsp_display_upd_value("PcieRpClkReqSupport[7]", 1,
|
||||
original->PcieRpClkReqSupport[7],
|
||||
params->PcieRpClkReqSupport[7]);
|
||||
fsp_display_upd_value("PcieRpClkReqSupport[8]", 1,
|
||||
original->PcieRpClkReqSupport[8],
|
||||
params->PcieRpClkReqSupport[8]);
|
||||
fsp_display_upd_value("PcieRpClkReqSupport[9]", 1,
|
||||
original->PcieRpClkReqSupport[9],
|
||||
params->PcieRpClkReqSupport[9]);
|
||||
fsp_display_upd_value("PcieRpClkReqSupport[10]", 1,
|
||||
original->PcieRpClkReqSupport[10],
|
||||
params->PcieRpClkReqSupport[10]);
|
||||
fsp_display_upd_value("PcieRpClkReqSupport[11]", 1,
|
||||
original->PcieRpClkReqSupport[11],
|
||||
params->PcieRpClkReqSupport[11]);
|
||||
fsp_display_upd_value("PcieRpClkReqSupport[12]", 1,
|
||||
original->PcieRpClkReqSupport[12],
|
||||
params->PcieRpClkReqSupport[12]);
|
||||
fsp_display_upd_value("PcieRpClkReqSupport[13]", 1,
|
||||
original->PcieRpClkReqSupport[13],
|
||||
params->PcieRpClkReqSupport[13]);
|
||||
fsp_display_upd_value("PcieRpClkReqSupport[14]", 1,
|
||||
original->PcieRpClkReqSupport[14],
|
||||
params->PcieRpClkReqSupport[14]);
|
||||
fsp_display_upd_value("PcieRpClkReqSupport[15]", 1,
|
||||
original->PcieRpClkReqSupport[15],
|
||||
params->PcieRpClkReqSupport[15]);
|
||||
fsp_display_upd_value("PcieRpClkReqSupport[16]", 1,
|
||||
original->PcieRpClkReqSupport[16],
|
||||
params->PcieRpClkReqSupport[16]);
|
||||
fsp_display_upd_value("PcieRpClkReqSupport[17]", 1,
|
||||
original->PcieRpClkReqSupport[17],
|
||||
params->PcieRpClkReqSupport[17]);
|
||||
fsp_display_upd_value("PcieRpClkReqSupport[18]", 1,
|
||||
original->PcieRpClkReqSupport[18],
|
||||
params->PcieRpClkReqSupport[18]);
|
||||
fsp_display_upd_value("PcieRpClkReqSupport[19]", 1,
|
||||
original->PcieRpClkReqSupport[19],
|
||||
params->PcieRpClkReqSupport[19]);
|
||||
fsp_display_upd_value("PcieRpClkReqNumber[0]", 1,
|
||||
original->PcieRpClkReqNumber[0],
|
||||
params->PcieRpClkReqNumber[0]);
|
||||
fsp_display_upd_value("PcieRpClkReqNumber[1]", 1,
|
||||
original->PcieRpClkReqNumber[1],
|
||||
params->PcieRpClkReqNumber[1]);
|
||||
fsp_display_upd_value("PcieRpClkReqNumber[2]", 1,
|
||||
original->PcieRpClkReqNumber[2],
|
||||
params->PcieRpClkReqNumber[2]);
|
||||
fsp_display_upd_value("PcieRpClkReqNumber[3]", 1,
|
||||
original->PcieRpClkReqNumber[3],
|
||||
params->PcieRpClkReqNumber[3]);
|
||||
fsp_display_upd_value("PcieRpClkReqNumber[4]", 1,
|
||||
original->PcieRpClkReqNumber[4],
|
||||
params->PcieRpClkReqNumber[4]);
|
||||
fsp_display_upd_value("PcieRpClkReqNumber[5]", 1,
|
||||
original->PcieRpClkReqNumber[5],
|
||||
params->PcieRpClkReqNumber[5]);
|
||||
fsp_display_upd_value("PcieRpClkReqNumber[6]", 1,
|
||||
original->PcieRpClkReqNumber[6],
|
||||
params->PcieRpClkReqNumber[6]);
|
||||
fsp_display_upd_value("PcieRpClkReqNumber[7]", 1,
|
||||
original->PcieRpClkReqNumber[7],
|
||||
params->PcieRpClkReqNumber[7]);
|
||||
fsp_display_upd_value("PcieRpClkReqNumber[8]", 1,
|
||||
original->PcieRpClkReqNumber[8],
|
||||
params->PcieRpClkReqNumber[8]);
|
||||
fsp_display_upd_value("PcieRpClkReqNumber[9]", 1,
|
||||
original->PcieRpClkReqNumber[9],
|
||||
params->PcieRpClkReqNumber[9]);
|
||||
fsp_display_upd_value("PcieRpClkReqNumber[10]", 1,
|
||||
original->PcieRpClkReqNumber[10],
|
||||
params->PcieRpClkReqNumber[10]);
|
||||
fsp_display_upd_value("PcieRpClkReqNumber[11]", 1,
|
||||
original->PcieRpClkReqNumber[11],
|
||||
params->PcieRpClkReqNumber[11]);
|
||||
fsp_display_upd_value("PcieRpClkReqNumber[12]", 1,
|
||||
original->PcieRpClkReqNumber[12],
|
||||
params->PcieRpClkReqNumber[12]);
|
||||
fsp_display_upd_value("PcieRpClkReqNumber[13]", 1,
|
||||
original->PcieRpClkReqNumber[13],
|
||||
params->PcieRpClkReqNumber[13]);
|
||||
fsp_display_upd_value("PcieRpClkReqNumber[14]", 1,
|
||||
original->PcieRpClkReqNumber[14],
|
||||
params->PcieRpClkReqNumber[14]);
|
||||
fsp_display_upd_value("PcieRpClkReqNumber[15]", 1,
|
||||
original->PcieRpClkReqNumber[15],
|
||||
params->PcieRpClkReqNumber[15]);
|
||||
fsp_display_upd_value("PcieRpClkReqNumber[16]", 1,
|
||||
original->PcieRpClkReqNumber[16],
|
||||
params->PcieRpClkReqNumber[16]);
|
||||
fsp_display_upd_value("PcieRpClkReqNumber[17]", 1,
|
||||
original->PcieRpClkReqNumber[17],
|
||||
params->PcieRpClkReqNumber[17]);
|
||||
fsp_display_upd_value("PcieRpClkReqNumber[18]", 1,
|
||||
original->PcieRpClkReqNumber[18],
|
||||
params->PcieRpClkReqNumber[18]);
|
||||
fsp_display_upd_value("PcieRpClkReqNumber[19]", 1,
|
||||
original->PcieRpClkReqNumber[19],
|
||||
params->PcieRpClkReqNumber[19]);
|
||||
fsp_display_upd_value("EnableLan", 1, original->EnableLan,
|
||||
params->EnableLan);
|
||||
fsp_display_upd_value("Cio2Enable", 1, original->Cio2Enable,
|
||||
params->Cio2Enable);
|
||||
fsp_display_upd_value("SataSalpSupport", 1, original->SataSalpSupport,
|
||||
params->SataSalpSupport);
|
||||
fsp_display_upd_value("SataPortsEnable[0]", 1,
|
||||
original->SataPortsEnable[0], params->SataPortsEnable[0]);
|
||||
fsp_display_upd_value("SataPortsEnable[1]", 1,
|
||||
original->SataPortsEnable[1], params->SataPortsEnable[1]);
|
||||
fsp_display_upd_value("SataPortsEnable[2]", 1,
|
||||
original->SataPortsEnable[2], params->SataPortsEnable[2]);
|
||||
fsp_display_upd_value("SataPortsEnable[3]", 1,
|
||||
original->SataPortsEnable[3], params->SataPortsEnable[3]);
|
||||
fsp_display_upd_value("SataPortsEnable[4]", 1,
|
||||
original->SataPortsEnable[4], params->SataPortsEnable[4]);
|
||||
fsp_display_upd_value("SataPortsEnable[5]", 1,
|
||||
original->SataPortsEnable[5], params->SataPortsEnable[5]);
|
||||
fsp_display_upd_value("SataPortsEnable[6]", 1,
|
||||
original->SataPortsEnable[6], params->SataPortsEnable[6]);
|
||||
fsp_display_upd_value("SataPortsEnable[7]", 1,
|
||||
original->SataPortsEnable[7], params->SataPortsEnable[7]);
|
||||
fsp_display_upd_value("SataPortsDevSlp[0]", 1,
|
||||
original->SataPortsDevSlp[0], params->SataPortsDevSlp[0]);
|
||||
fsp_display_upd_value("SataPortsDevSlp[1]", 1,
|
||||
original->SataPortsDevSlp[1], params->SataPortsDevSlp[1]);
|
||||
fsp_display_upd_value("SataPortsDevSlp[2]", 1,
|
||||
original->SataPortsDevSlp[2], params->SataPortsDevSlp[2]);
|
||||
fsp_display_upd_value("SataPortsDevSlp[3]", 1,
|
||||
original->SataPortsDevSlp[3], params->SataPortsDevSlp[3]);
|
||||
fsp_display_upd_value("SataPortsDevSlp[4]", 1,
|
||||
original->SataPortsDevSlp[4], params->SataPortsDevSlp[4]);
|
||||
fsp_display_upd_value("SataPortsDevSlp[5]", 1,
|
||||
original->SataPortsDevSlp[5], params->SataPortsDevSlp[5]);
|
||||
fsp_display_upd_value("SataPortsDevSlp[6]", 1,
|
||||
original->SataPortsDevSlp[6], params->SataPortsDevSlp[6]);
|
||||
fsp_display_upd_value("SataPortsDevSlp[7]", 1,
|
||||
original->SataPortsDevSlp[7], params->SataPortsDevSlp[7]);
|
||||
fsp_display_upd_value("EnableAzalia", 1,
|
||||
original->EnableAzalia, params->EnableAzalia);
|
||||
fsp_display_upd_value("DspEnable", 1, original->DspEnable,
|
||||
params->DspEnable);
|
||||
fsp_display_upd_value("IoBufferOwnership", 1,
|
||||
original->IoBufferOwnership, params->IoBufferOwnership);
|
||||
fsp_display_upd_value("PortUsb20Enable[0]", 1,
|
||||
original->PortUsb20Enable[0], params->PortUsb20Enable[0]);
|
||||
fsp_display_upd_value("PortUsb20Enable[1]", 1,
|
||||
original->PortUsb20Enable[1], params->PortUsb20Enable[1]);
|
||||
fsp_display_upd_value("PortUsb20Enable[2]", 1,
|
||||
original->PortUsb20Enable[2], params->PortUsb20Enable[2]);
|
||||
fsp_display_upd_value("PortUsb20Enable[3]", 1,
|
||||
original->PortUsb20Enable[3], params->PortUsb20Enable[3]);
|
||||
fsp_display_upd_value("PortUsb20Enable[4]", 1,
|
||||
original->PortUsb20Enable[4], params->PortUsb20Enable[4]);
|
||||
fsp_display_upd_value("PortUsb20Enable[5]", 1,
|
||||
original->PortUsb20Enable[5], params->PortUsb20Enable[5]);
|
||||
fsp_display_upd_value("PortUsb20Enable[6]", 1,
|
||||
original->PortUsb20Enable[6], params->PortUsb20Enable[6]);
|
||||
fsp_display_upd_value("PortUsb20Enable[7]", 1,
|
||||
original->PortUsb20Enable[7], params->PortUsb20Enable[7]);
|
||||
fsp_display_upd_value("PortUsb20Enable[8]", 1,
|
||||
original->PortUsb20Enable[8], params->PortUsb20Enable[8]);
|
||||
fsp_display_upd_value("PortUsb20Enable[9]", 1,
|
||||
original->PortUsb20Enable[9], params->PortUsb20Enable[9]);
|
||||
fsp_display_upd_value("PortUsb20Enable[10]", 1,
|
||||
original->PortUsb20Enable[10], params->PortUsb20Enable[10]);
|
||||
fsp_display_upd_value("PortUsb20Enable[11]", 1,
|
||||
original->PortUsb20Enable[11], params->PortUsb20Enable[11]);
|
||||
fsp_display_upd_value("PortUsb20Enable[12]", 1,
|
||||
original->PortUsb20Enable[12], params->PortUsb20Enable[12]);
|
||||
fsp_display_upd_value("PortUsb20Enable[13]", 1,
|
||||
original->PortUsb20Enable[13], params->PortUsb20Enable[13]);
|
||||
fsp_display_upd_value("PortUsb20Enable[14]", 1,
|
||||
original->PortUsb20Enable[14], params->PortUsb20Enable[14]);
|
||||
fsp_display_upd_value("PortUsb20Enable[15]", 1,
|
||||
original->PortUsb20Enable[15], params->PortUsb20Enable[15]);
|
||||
fsp_display_upd_value("PortUsb30Enable[0]", 1,
|
||||
original->PortUsb30Enable[0], params->PortUsb30Enable[0]);
|
||||
fsp_display_upd_value("PortUsb30Enable[1]", 1,
|
||||
original->PortUsb30Enable[1], params->PortUsb30Enable[1]);
|
||||
fsp_display_upd_value("PortUsb30Enable[2]", 1,
|
||||
original->PortUsb30Enable[2], params->PortUsb30Enable[2]);
|
||||
fsp_display_upd_value("PortUsb30Enable[3]", 1,
|
||||
original->PortUsb30Enable[3], params->PortUsb30Enable[3]);
|
||||
fsp_display_upd_value("PortUsb30Enable[4]", 1,
|
||||
original->PortUsb30Enable[4], params->PortUsb30Enable[4]);
|
||||
fsp_display_upd_value("PortUsb30Enable[5]", 1,
|
||||
original->PortUsb30Enable[5], params->PortUsb30Enable[5]);
|
||||
fsp_display_upd_value("PortUsb30Enable[6]", 1,
|
||||
original->PortUsb30Enable[6], params->PortUsb30Enable[6]);
|
||||
fsp_display_upd_value("PortUsb30Enable[7]", 1,
|
||||
original->PortUsb30Enable[7], params->PortUsb30Enable[7]);
|
||||
fsp_display_upd_value("PortUsb30Enable[8]", 1,
|
||||
original->PortUsb30Enable[8], params->PortUsb30Enable[8]);
|
||||
fsp_display_upd_value("PortUsb30Enable[9]", 1,
|
||||
original->PortUsb30Enable[9], params->PortUsb30Enable[9]);
|
||||
fsp_display_upd_value("XdciEnable", 1, original->XdciEnable,
|
||||
params->XdciEnable);
|
||||
fsp_display_upd_value("SsicPortEnable", 1, original->SsicPortEnable,
|
||||
params->SsicPortEnable);
|
||||
fsp_display_upd_value("SmbusEnable", 1, original->SmbusEnable,
|
||||
params->SmbusEnable);
|
||||
fsp_display_upd_value("SerialIoDevMode[0]", 1,
|
||||
original->SerialIoDevMode[0], params->SerialIoDevMode[0]);
|
||||
fsp_display_upd_value("SerialIoDevMode[1]", 1,
|
||||
original->SerialIoDevMode[1], params->SerialIoDevMode[1]);
|
||||
fsp_display_upd_value("SerialIoDevMode[2]", 1,
|
||||
original->SerialIoDevMode[2], params->SerialIoDevMode[2]);
|
||||
fsp_display_upd_value("SerialIoDevMode[3]", 1,
|
||||
original->SerialIoDevMode[3], params->SerialIoDevMode[3]);
|
||||
fsp_display_upd_value("SerialIoDevMode[4]", 1,
|
||||
original->SerialIoDevMode[4], params->SerialIoDevMode[4]);
|
||||
fsp_display_upd_value("SerialIoDevMode[5]", 1,
|
||||
original->SerialIoDevMode[5], params->SerialIoDevMode[5]);
|
||||
fsp_display_upd_value("SerialIoDevMode[6]", 1,
|
||||
original->SerialIoDevMode[6], params->SerialIoDevMode[6]);
|
||||
fsp_display_upd_value("SerialIoDevMode[7]", 1,
|
||||
original->SerialIoDevMode[7], params->SerialIoDevMode[7]);
|
||||
fsp_display_upd_value("SerialIoDevMode[8]", 1,
|
||||
original->SerialIoDevMode[8], params->SerialIoDevMode[8]);
|
||||
fsp_display_upd_value("SerialIoDevMode[9]", 1,
|
||||
original->SerialIoDevMode[9], params->SerialIoDevMode[9]);
|
||||
fsp_display_upd_value("SerialIoDevMode[10]", 1,
|
||||
original->SerialIoDevMode[10], params->SerialIoDevMode[10]);
|
||||
fsp_display_upd_value("ScsEmmcEnabled", 1, original->ScsEmmcEnabled,
|
||||
params->ScsEmmcEnabled);
|
||||
fsp_display_upd_value("ScsEmmcHs400Enabled", 1,
|
||||
original->ScsEmmcHs400Enabled, params->ScsEmmcHs400Enabled);
|
||||
fsp_display_upd_value("ScsSdCardEnabled", 1, original->ScsSdCardEnabled,
|
||||
params->ScsSdCardEnabled);
|
||||
fsp_display_upd_value("IshEnable", 1, original->IshEnable,
|
||||
params->IshEnable);
|
||||
fsp_display_upd_value("ShowSpiController", 1,
|
||||
original->ShowSpiController, params->ShowSpiController);
|
||||
fsp_display_upd_value("HsioMessaging", 1, original->HsioMessaging,
|
||||
params->HsioMessaging);
|
||||
fsp_display_upd_value("Heci3Enabled", 1, original->Heci3Enabled,
|
||||
params->Heci3Enabled);
|
||||
fsp_display_upd_value("EnableSata", 1, original->EnableSata,
|
||||
params->EnableSata);
|
||||
fsp_display_upd_value("SataMode", 1, original->SataMode,
|
||||
params->SataMode);
|
||||
fsp_display_upd_value("NumOfDevIntConfig", 1,
|
||||
original->NumOfDevIntConfig,
|
||||
params->NumOfDevIntConfig);
|
||||
fsp_display_upd_value("PxRcConfig[PARC]", 1,
|
||||
original->PxRcConfig[PCH_PARC],
|
||||
params->PxRcConfig[PCH_PARC]);
|
||||
fsp_display_upd_value("PxRcConfig[PBRC]", 1,
|
||||
original->PxRcConfig[PCH_PBRC],
|
||||
params->PxRcConfig[PCH_PBRC]);
|
||||
fsp_display_upd_value("PxRcConfig[PCRC]", 1,
|
||||
original->PxRcConfig[PCH_PCRC],
|
||||
params->PxRcConfig[PCH_PCRC]);
|
||||
fsp_display_upd_value("PxRcConfig[PDRC]", 1,
|
||||
original->PxRcConfig[PCH_PDRC],
|
||||
params->PxRcConfig[PCH_PDRC]);
|
||||
fsp_display_upd_value("PxRcConfig[PERC]", 1,
|
||||
original->PxRcConfig[PCH_PERC],
|
||||
params->PxRcConfig[PCH_PERC]);
|
||||
fsp_display_upd_value("PxRcConfig[PFRC]", 1,
|
||||
original->PxRcConfig[PCH_PFRC],
|
||||
params->PxRcConfig[PCH_PFRC]);
|
||||
fsp_display_upd_value("PxRcConfig[PGRC]", 1,
|
||||
original->PxRcConfig[PCH_PGRC],
|
||||
params->PxRcConfig[PCH_PGRC]);
|
||||
fsp_display_upd_value("PxRcConfig[PHRC]", 1,
|
||||
original->PxRcConfig[PCH_PHRC],
|
||||
params->PxRcConfig[PCH_PHRC]);
|
||||
fsp_display_upd_value("GpioIrqRoute", 1,
|
||||
original->GpioIrqRoute,
|
||||
params->GpioIrqRoute);
|
||||
fsp_display_upd_value("SciIrqSelect", 1,
|
||||
original->SciIrqSelect,
|
||||
params->SciIrqSelect);
|
||||
fsp_display_upd_value("TcoIrqSelect", 1,
|
||||
original->TcoIrqSelect,
|
||||
params->TcoIrqSelect);
|
||||
fsp_display_upd_value("TcoIrqEnable", 1,
|
||||
original->TcoIrqEnable,
|
||||
params->TcoIrqEnable);
|
||||
fsp_display_upd_value("LockDownConfigGlobalSmi", 1,
|
||||
original->LockDownConfigGlobalSmi,
|
||||
params->LockDownConfigGlobalSmi);
|
||||
fsp_display_upd_value("LockDownConfigBiosInterface", 1,
|
||||
original->LockDownConfigBiosInterface,
|
||||
params->LockDownConfigBiosInterface);
|
||||
fsp_display_upd_value("LockDownConfigRtcLock", 1,
|
||||
original->LockDownConfigRtcLock,
|
||||
params->LockDownConfigRtcLock);
|
||||
fsp_display_upd_value("LockDownConfigBiosLock", 1,
|
||||
original->LockDownConfigBiosLock,
|
||||
params->LockDownConfigBiosLock);
|
||||
fsp_display_upd_value("LockDownConfigSpiEiss", 1,
|
||||
original->LockDownConfigSpiEiss,
|
||||
params->LockDownConfigSpiEiss);
|
||||
fsp_display_upd_value("PchConfigSubSystemVendorId", 1,
|
||||
original->PchConfigSubSystemVendorId,
|
||||
params->PchConfigSubSystemVendorId);
|
||||
fsp_display_upd_value("PchConfigSubSystemId", 1,
|
||||
original->PchConfigSubSystemId,
|
||||
params->PchConfigSubSystemId);
|
||||
fsp_display_upd_value("WakeConfigWolEnableOverride", 1,
|
||||
original->WakeConfigWolEnableOverride,
|
||||
params->WakeConfigWolEnableOverride);
|
||||
fsp_display_upd_value("WakeConfigPcieWakeFromDeepSx", 1,
|
||||
original->WakeConfigPcieWakeFromDeepSx,
|
||||
params->WakeConfigPcieWakeFromDeepSx);
|
||||
fsp_display_upd_value("PmConfigDeepSxPol", 1,
|
||||
original->PmConfigDeepSxPol,
|
||||
params->PmConfigDeepSxPol);
|
||||
fsp_display_upd_value("PmConfigSlpS3MinAssert", 1,
|
||||
original->PmConfigSlpS3MinAssert,
|
||||
params->PmConfigSlpS3MinAssert);
|
||||
fsp_display_upd_value("PmConfigSlpS4MinAssert", 1,
|
||||
original->PmConfigSlpS4MinAssert,
|
||||
params->PmConfigSlpS4MinAssert);
|
||||
fsp_display_upd_value("PmConfigSlpSusMinAssert", 1,
|
||||
original->PmConfigSlpSusMinAssert,
|
||||
params->PmConfigSlpSusMinAssert);
|
||||
fsp_display_upd_value("PmConfigSlpAMinAssert", 1,
|
||||
original->PmConfigSlpAMinAssert,
|
||||
params->PmConfigSlpAMinAssert);
|
||||
fsp_display_upd_value("PmConfigPciClockRun", 1,
|
||||
original->PmConfigPciClockRun,
|
||||
params->PmConfigPciClockRun);
|
||||
fsp_display_upd_value("PmConfigSlpStrchSusUp", 1,
|
||||
original->PmConfigSlpStrchSusUp,
|
||||
params->PmConfigSlpStrchSusUp);
|
||||
fsp_display_upd_value("PmConfigPwrBtnOverridePeriod", 1,
|
||||
original->PmConfigPwrBtnOverridePeriod,
|
||||
params->PmConfigPwrBtnOverridePeriod);
|
||||
fsp_display_upd_value("PmConfigPwrCycDur", 1,
|
||||
original->PmConfigPwrCycDur,
|
||||
params->PmConfigPwrCycDur);
|
||||
fsp_display_upd_value("SerialIrqConfigSirqEnable", 1,
|
||||
original->SerialIrqConfigSirqEnable,
|
||||
params->SerialIrqConfigSirqEnable);
|
||||
fsp_display_upd_value("SerialIrqConfigSirqMode", 1,
|
||||
original->SerialIrqConfigSirqMode,
|
||||
params->SerialIrqConfigSirqMode);
|
||||
fsp_display_upd_value("SerialIrqConfigStartFramePulse", 1,
|
||||
original->SerialIrqConfigStartFramePulse,
|
||||
params->SerialIrqConfigStartFramePulse);
|
||||
|
||||
fsp_display_upd_value("Psi1Threshold[0]", 1,
|
||||
original->Psi1Threshold[0],
|
||||
params->Psi1Threshold[0]);
|
||||
fsp_display_upd_value("Psi1Threshold[1]", 1,
|
||||
original->Psi1Threshold[1],
|
||||
params->Psi1Threshold[1]);
|
||||
fsp_display_upd_value("Psi1Threshold[2]", 1,
|
||||
original->Psi1Threshold[2],
|
||||
params->Psi1Threshold[2]);
|
||||
fsp_display_upd_value("Psi1Threshold[3]", 1,
|
||||
original->Psi1Threshold[3],
|
||||
params->Psi1Threshold[3]);
|
||||
fsp_display_upd_value("Psi1Threshold[4]", 1,
|
||||
original->Psi1Threshold[4],
|
||||
params->Psi1Threshold[4]);
|
||||
fsp_display_upd_value("Psi2Threshold[0]", 1,
|
||||
original->Psi2Threshold[0],
|
||||
params->Psi2Threshold[0]);
|
||||
fsp_display_upd_value("Psi2Threshold[1]", 1,
|
||||
original->Psi2Threshold[1],
|
||||
params->Psi2Threshold[1]);
|
||||
fsp_display_upd_value("Psi2Threshold[2]", 1,
|
||||
original->Psi2Threshold[2],
|
||||
params->Psi2Threshold[2]);
|
||||
fsp_display_upd_value("Psi2Threshold[3]", 1,
|
||||
original->Psi2Threshold[3],
|
||||
params->Psi2Threshold[3]);
|
||||
fsp_display_upd_value("Psi2Threshold[4]", 1,
|
||||
original->Psi2Threshold[4],
|
||||
params->Psi2Threshold[4]);
|
||||
fsp_display_upd_value("Psi3Threshold[0]", 1,
|
||||
original->Psi3Threshold[0],
|
||||
params->Psi3Threshold[0]);
|
||||
fsp_display_upd_value("Psi3Threshold[1]", 1,
|
||||
original->Psi3Threshold[1],
|
||||
params->Psi3Threshold[1]);
|
||||
fsp_display_upd_value("Psi3Threshold[2]", 1,
|
||||
original->Psi3Threshold[2],
|
||||
params->Psi3Threshold[2]);
|
||||
fsp_display_upd_value("Psi3Threshold[3]", 1,
|
||||
original->Psi3Threshold[3],
|
||||
params->Psi3Threshold[3]);
|
||||
fsp_display_upd_value("Psi3Threshold[4]", 1,
|
||||
original->Psi3Threshold[4],
|
||||
params->Psi3Threshold[4]);
|
||||
fsp_display_upd_value("Psi3Enable[0]", 1,
|
||||
original->Psi3Enable[0],
|
||||
params->Psi3Enable[0]);
|
||||
fsp_display_upd_value("Psi3Enable[1]", 1,
|
||||
original->Psi3Enable[1],
|
||||
params->Psi3Enable[1]);
|
||||
fsp_display_upd_value("Psi3Enable[2]", 1,
|
||||
original->Psi3Enable[2],
|
||||
params->Psi3Enable[2]);
|
||||
fsp_display_upd_value("Psi3Enable[3]", 1,
|
||||
original->Psi3Enable[3],
|
||||
params->Psi3Enable[3]);
|
||||
fsp_display_upd_value("Psi3Enable[4]", 1,
|
||||
original->Psi3Enable[4],
|
||||
params->Psi3Enable[4]);
|
||||
fsp_display_upd_value("Psi4Enable[0]", 1,
|
||||
original->Psi4Enable[0],
|
||||
params->Psi4Enable[0]);
|
||||
fsp_display_upd_value("Psi4Enable[1]", 1,
|
||||
original->Psi4Enable[1],
|
||||
params->Psi4Enable[1]);
|
||||
fsp_display_upd_value("Psi4Enable[2]", 1,
|
||||
original->Psi4Enable[2],
|
||||
params->Psi4Enable[2]);
|
||||
fsp_display_upd_value("Psi4Enable[3]", 1,
|
||||
original->Psi4Enable[3],
|
||||
params->Psi4Enable[3]);
|
||||
fsp_display_upd_value("Psi4Enable[4]", 1,
|
||||
original->Psi4Enable[4],
|
||||
params->Psi4Enable[4]);
|
||||
fsp_display_upd_value("ImonSlope[0]", 1,
|
||||
original->ImonSlope[0],
|
||||
params->ImonSlope[0]);
|
||||
fsp_display_upd_value("ImonSlope[1]", 1,
|
||||
original->ImonSlope[1],
|
||||
params->ImonSlope[1]);
|
||||
fsp_display_upd_value("ImonSlope[2]", 1,
|
||||
original->ImonSlope[2],
|
||||
params->ImonSlope[2]);
|
||||
fsp_display_upd_value("ImonSlope[3]", 1,
|
||||
original->ImonSlope[3],
|
||||
params->ImonSlope[3]);
|
||||
fsp_display_upd_value("ImonSlope[4]", 1,
|
||||
original->ImonSlope[4],
|
||||
params->ImonSlope[4]);
|
||||
fsp_display_upd_value("ImonOffse[0]t", 1,
|
||||
original->ImonOffset[0],
|
||||
params->ImonOffset[0]);
|
||||
fsp_display_upd_value("ImonOffse[1]t", 1,
|
||||
original->ImonOffset[1],
|
||||
params->ImonOffset[1]);
|
||||
fsp_display_upd_value("ImonOffse[2]t", 1,
|
||||
original->ImonOffset[2],
|
||||
params->ImonOffset[2]);
|
||||
fsp_display_upd_value("ImonOffse[3]t", 1,
|
||||
original->ImonOffset[3],
|
||||
params->ImonOffset[3]);
|
||||
fsp_display_upd_value("ImonOffse[4]t", 1,
|
||||
original->ImonOffset[4],
|
||||
params->ImonOffset[4]);
|
||||
fsp_display_upd_value("IccMax[0]", 1,
|
||||
original->IccMax[0],
|
||||
params->IccMax[0]);
|
||||
fsp_display_upd_value("IccMax[1]", 1,
|
||||
original->IccMax[1],
|
||||
params->IccMax[1]);
|
||||
fsp_display_upd_value("IccMax[2]", 1,
|
||||
original->IccMax[2],
|
||||
params->IccMax[2]);
|
||||
fsp_display_upd_value("IccMax[3]", 1,
|
||||
original->IccMax[3],
|
||||
params->IccMax[3]);
|
||||
fsp_display_upd_value("IccMax[4]", 1,
|
||||
original->IccMax[4],
|
||||
params->IccMax[4]);
|
||||
fsp_display_upd_value("VrVoltageLimit[0]", 1,
|
||||
original->VrVoltageLimit[0],
|
||||
params->VrVoltageLimit[0]);
|
||||
fsp_display_upd_value("VrVoltageLimit[1]", 1,
|
||||
original->VrVoltageLimit[1],
|
||||
params->VrVoltageLimit[1]);
|
||||
fsp_display_upd_value("VrVoltageLimit[2]", 1,
|
||||
original->VrVoltageLimit[2],
|
||||
params->VrVoltageLimit[2]);
|
||||
fsp_display_upd_value("VrVoltageLimit[3]", 1,
|
||||
original->VrVoltageLimit[3],
|
||||
params->VrVoltageLimit[3]);
|
||||
fsp_display_upd_value("VrVoltageLimit[4]", 1,
|
||||
original->VrVoltageLimit[4],
|
||||
params->VrVoltageLimit[4]);
|
||||
fsp_display_upd_value("VrConfigEnable[0]", 1,
|
||||
original->VrConfigEnable[0],
|
||||
params->VrConfigEnable[0]);
|
||||
fsp_display_upd_value("VrConfigEnable[1]", 1,
|
||||
original->VrConfigEnable[1],
|
||||
params->VrConfigEnable[1]);
|
||||
fsp_display_upd_value("VrConfigEnable[2]", 1,
|
||||
original->VrConfigEnable[2],
|
||||
params->VrConfigEnable[2]);
|
||||
fsp_display_upd_value("VrConfigEnable[3]", 1,
|
||||
original->VrConfigEnable[3],
|
||||
params->VrConfigEnable[3]);
|
||||
fsp_display_upd_value("VrConfigEnable[4]", 1,
|
||||
original->VrConfigEnable[4],
|
||||
params->VrConfigEnable[4]);
|
||||
fsp_display_upd_value("SerialIoI2cVoltage[0]", 1,
|
||||
original->SerialIoI2cVoltage[0],
|
||||
params->SerialIoI2cVoltage[0]);
|
||||
fsp_display_upd_value("SerialIoI2cVoltage[1]", 1,
|
||||
original->SerialIoI2cVoltage[1],
|
||||
params->SerialIoI2cVoltage[1]);
|
||||
fsp_display_upd_value("SerialIoI2cVoltage[2]", 1,
|
||||
original->SerialIoI2cVoltage[2],
|
||||
params->SerialIoI2cVoltage[2]);
|
||||
fsp_display_upd_value("SerialIoI2cVoltage[3]", 1,
|
||||
original->SerialIoI2cVoltage[3],
|
||||
params->SerialIoI2cVoltage[3]);
|
||||
fsp_display_upd_value("SerialIoI2cVoltage[4]", 1,
|
||||
original->SerialIoI2cVoltage[4],
|
||||
params->SerialIoI2cVoltage[4]);
|
||||
fsp_display_upd_value("SerialIoI2cVoltage[5]", 1,
|
||||
original->SerialIoI2cVoltage[5],
|
||||
params->SerialIoI2cVoltage[5]);
|
||||
fsp_display_upd_value("SendVrMbxCmd", 1,
|
||||
original->SendVrMbxCmd,
|
||||
params->SendVrMbxCmd);
|
||||
fsp_display_upd_value("AcousticNoiseMitigation", 1,
|
||||
original->AcousticNoiseMitigation,
|
||||
params->AcousticNoiseMitigation);
|
||||
fsp_display_upd_value("SlowSlewRateForIa", 1,
|
||||
original->SlowSlewRateForIa,
|
||||
params->SlowSlewRateForIa);
|
||||
fsp_display_upd_value("SlowSlewRateForGt", 1,
|
||||
original->SlowSlewRateForGt,
|
||||
params->SlowSlewRateForGt);
|
||||
fsp_display_upd_value("SlowSlewRateForSa", 1,
|
||||
original->SlowSlewRateForSa,
|
||||
params->SlowSlewRateForSa);
|
||||
fsp_display_upd_value("FastPkgCRampDisable", 1,
|
||||
original->FastPkgCRampDisable,
|
||||
params->FastPkgCRampDisable);
|
||||
}
|
||||
|
|
@ -1,37 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
* Copyright (C) 2015-2017 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _SOC_RAMSTAGE_H_
|
||||
#define _SOC_RAMSTAGE_H_
|
||||
|
||||
#include <device/device.h>
|
||||
#include <fsp/ramstage.h>
|
||||
#include <fsp/soc_binding.h>
|
||||
|
||||
#include "../../../chip.h"
|
||||
|
||||
#define FSP_SIL_UPD SILICON_INIT_UPD
|
||||
#define FSP_MEM_UPD MEMORY_INIT_UPD
|
||||
|
||||
void soc_irq_settings(FSP_SIL_UPD *params);
|
||||
void soc_init_pre_device(void *chip_info);
|
||||
void soc_fsp_load(void);
|
||||
const char *soc_acpi_name(const struct device *dev);
|
||||
|
||||
/* Get igd framebuffer bar */
|
||||
uintptr_t fsp_soc_get_igd_bar(void);
|
||||
|
||||
#endif
|
||||
|
|
@ -1,27 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
* Copyright (C) 2015-2016 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _SOC_ROMSTAGE_H_
|
||||
#define _SOC_ROMSTAGE_H_
|
||||
|
||||
#include <fsp/romstage.h>
|
||||
|
||||
void systemagent_early_init(void);
|
||||
void intel_early_me_status(void);
|
||||
void enable_smbus(void);
|
||||
int smbus_read_byte(unsigned int device, unsigned int address);
|
||||
|
||||
#endif /* _SOC_ROMSTAGE_H_ */
|
||||
|
|
@ -18,12 +18,6 @@
|
|||
|
||||
#include <intelblocks/systemagent.h>
|
||||
|
||||
#if CONFIG(PLATFORM_USES_FSP1_1)
|
||||
#include <fsp/bootblock.h>
|
||||
#else
|
||||
static inline void bootblock_fsp_temp_ram_init(void) {}
|
||||
#endif
|
||||
|
||||
/* Bootblock pre console init programming */
|
||||
void bootblock_cpu_init(void);
|
||||
void bootblock_pch_early_init(void);
|
||||
|
|
|
|||
|
|
@ -169,14 +169,6 @@ struct chipset_power_state {
|
|||
uint32_t prev_sleep_state;
|
||||
} __packed;
|
||||
|
||||
/*
|
||||
* This is used only in FSP1_1 as we wanted to keep the flow unchanged.
|
||||
* Internally fill_power_state calls the new pmc_fill_power_state now
|
||||
*/
|
||||
#if CONFIG(PLATFORM_USES_FSP1_1)
|
||||
struct chipset_power_state *fill_power_state(void);
|
||||
#endif
|
||||
|
||||
/* Return the selected ACPI SCI IRQ */
|
||||
int acpi_sci_irq(void);
|
||||
|
||||
|
|
|
|||
|
|
@ -19,11 +19,7 @@
|
|||
#ifndef _SOC_VR_CONFIG_H_
|
||||
#define _SOC_VR_CONFIG_H_
|
||||
|
||||
#if CONFIG(PLATFORM_USES_FSP1_1)
|
||||
#include <fsp/soc_binding.h>
|
||||
#else
|
||||
#include <fsp/api.h>
|
||||
#endif
|
||||
|
||||
struct vr_config {
|
||||
|
||||
|
|
@ -70,30 +66,6 @@ struct vr_config {
|
|||
#define VR_CFG_AMP(i) ((i) * 4)
|
||||
#define VR_CFG_MOHMS(i) (uint16_t)((i) * 100)
|
||||
|
||||
#if CONFIG(PLATFORM_USES_FSP1_1)
|
||||
/* VrConfig Settings for 5 domains
|
||||
* 0 = System Agent, 1 = IA Core, 2 = Ring,
|
||||
* 3 = GT unsliced, 4 = GT sliced
|
||||
*/
|
||||
enum vr_domain {
|
||||
VR_SYSTEM_AGENT,
|
||||
VR_IA_CORE,
|
||||
VR_RING,
|
||||
VR_GT_UNSLICED,
|
||||
VR_GT_SLICED,
|
||||
NUM_VR_DOMAINS
|
||||
};
|
||||
|
||||
#define VR_CFG_ALL_DOMAINS_ICC(sa, ia, gt_unsl, gt_sl) \
|
||||
{ \
|
||||
[VR_SYSTEM_AGENT] = VR_CFG_AMP(sa), \
|
||||
[VR_IA_CORE] = VR_CFG_AMP(ia), \
|
||||
[VR_RING] = VR_CFG_AMP(0), \
|
||||
[VR_GT_UNSLICED] = VR_CFG_AMP(gt_unsl), \
|
||||
[VR_GT_SLICED] = VR_CFG_AMP(gt_sl), \
|
||||
}
|
||||
|
||||
#else
|
||||
/* VrConfig Settings for 4 domains
|
||||
* 0 = System Agent, 1 = IA Core,
|
||||
* 2 = GT unsliced, 3 = GT sliced
|
||||
|
|
@ -114,8 +86,6 @@ enum vr_domain {
|
|||
[VR_GT_SLICED] = VR_CFG_AMP(gt_sl), \
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#define VR_CFG_ALL_DOMAINS_LOADLINE(sa, ia, gt_unsl, gt_sl) \
|
||||
{ \
|
||||
[VR_SYSTEM_AGENT] = VR_CFG_MOHMS(sa), \
|
||||
|
|
|
|||
|
|
@ -84,12 +84,7 @@ static size_t get_prmrr_size(uintptr_t dram_base,
|
|||
const struct soc_intel_skylake_config *config)
|
||||
{
|
||||
uintptr_t prmrr_base = dram_base;
|
||||
size_t prmrr_size;
|
||||
|
||||
if (CONFIG(PLATFORM_USES_FSP1_1))
|
||||
prmrr_size = 1*MiB;
|
||||
else
|
||||
prmrr_size = config->PrmrrSize;
|
||||
size_t prmrr_size = config->PrmrrSize;
|
||||
|
||||
if (!prmrr_size)
|
||||
return 0;
|
||||
|
|
@ -292,7 +287,6 @@ void *cbmem_top(void)
|
|||
return (void *)(uintptr_t)ebda_cfg.tolum_base;
|
||||
}
|
||||
|
||||
#if CONFIG(PLATFORM_USES_FSP2_0)
|
||||
void fill_postcar_frame(struct postcar_frame *pcf)
|
||||
{
|
||||
uintptr_t top_of_ram;
|
||||
|
|
@ -311,4 +305,3 @@ void fill_postcar_frame(struct postcar_frame *pcf)
|
|||
/* Cache the TSEG region */
|
||||
postcar_enable_tseg_cache(pcf);
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,4 +1,3 @@
|
|||
romstage-y += ../../../../cpu/intel/car/romstage.c
|
||||
romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c
|
||||
romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage_fsp20.c
|
||||
romstage-y += romstage_fsp20.c
|
||||
romstage-y += systemagent.c
|
||||
|
|
|
|||
|
|
@ -1,261 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/cbfs.h>
|
||||
#include <assert.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <intelblocks/fast_spi.h>
|
||||
#include <intelblocks/pmclib.h>
|
||||
#include <soc/pci_devs.h>
|
||||
#include <soc/pm.h>
|
||||
#include <soc/pmc.h>
|
||||
#include <soc/serialio.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <stage_cache.h>
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
#include <vendorcode/google/chromeos/chromeos.h>
|
||||
|
||||
#include "../chip.h"
|
||||
|
||||
/* SOC initialization before RAM is enabled */
|
||||
void soc_pre_ram_init(struct romstage_params *params)
|
||||
{
|
||||
const struct soc_intel_skylake_config *config;
|
||||
|
||||
/* Program MCHBAR and DMIBAR */
|
||||
systemagent_early_init();
|
||||
|
||||
config = config_of_soc();
|
||||
|
||||
/* Force a full memory train if RMT is enabled */
|
||||
params->disable_saved_data = config->Rmt;
|
||||
}
|
||||
|
||||
/* UPD parameters to be initialized before MemoryInit */
|
||||
void soc_memory_init_params(struct romstage_params *params,
|
||||
MEMORY_INIT_UPD *upd)
|
||||
{
|
||||
const struct soc_intel_skylake_config *config;
|
||||
|
||||
/* Set the parameters for MemoryInit */
|
||||
|
||||
config = config_of_soc();
|
||||
|
||||
/*
|
||||
* Set IGD stolen size to 64MB. The FBC hardware for skylake does not
|
||||
* have access to the bios_reserved range so it always assumes 8MB is
|
||||
* used and so the kernel will avoid the last 8MB of the stolen window.
|
||||
* With the default stolen size of 32MB(-8MB) there is not enough space
|
||||
* for FBC to work with a high resolution panel.
|
||||
*/
|
||||
upd->IgdDvmt50PreAlloc = 2;
|
||||
|
||||
upd->MmioSize = 0x800; /* 2GB in MB */
|
||||
upd->TsegSize = CONFIG_SMM_TSEG_SIZE;
|
||||
upd->IedSize = CONFIG_IED_REGION_SIZE;
|
||||
upd->ProbelessTrace = config->ProbelessTrace;
|
||||
upd->EnableTraceHub = config->EnableTraceHub;
|
||||
if (vboot_recovery_mode_enabled())
|
||||
upd->SaGv = 0; /* Disable SaGv in recovery mode. */
|
||||
else
|
||||
upd->SaGv = config->SaGv;
|
||||
upd->RMT = config->Rmt;
|
||||
upd->DdrFreqLimit = config->DdrFreqLimit;
|
||||
upd->FspCarBase = CONFIG_DCACHE_RAM_BASE;
|
||||
upd->FspCarSize = CONFIG_DCACHE_RAM_SIZE;
|
||||
}
|
||||
|
||||
void soc_update_memory_params_for_mma(MEMORY_INIT_UPD *memory_cfg,
|
||||
struct mma_config_param *mma_cfg)
|
||||
{
|
||||
/* Boot media is memory mapped for Skylake and Kabylake (SPI). */
|
||||
assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
|
||||
|
||||
memory_cfg->MmaTestContentPtr =
|
||||
(uintptr_t) rdev_mmap_full(&mma_cfg->test_content);
|
||||
memory_cfg->MmaTestContentSize =
|
||||
region_device_sz(&mma_cfg->test_content);
|
||||
memory_cfg->MmaTestConfigPtr =
|
||||
(uintptr_t) rdev_mmap_full(&mma_cfg->test_param);
|
||||
memory_cfg->MmaTestConfigSize =
|
||||
region_device_sz(&mma_cfg->test_param);
|
||||
memory_cfg->MrcFastBoot = 0x00;
|
||||
memory_cfg->SaGv = 0x02;
|
||||
}
|
||||
|
||||
void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
|
||||
MEMORY_INIT_UPD *new)
|
||||
{
|
||||
/* Display the parameters for MemoryInit */
|
||||
printk(BIOS_SPEW, "UPD values for MemoryInit:\n");
|
||||
|
||||
fsp_display_upd_value("PlatformMemorySize", 8,
|
||||
old->PlatformMemorySize, new->PlatformMemorySize);
|
||||
fsp_display_upd_value("MemorySpdPtr00", 4, old->MemorySpdPtr00,
|
||||
new->MemorySpdPtr00);
|
||||
fsp_display_upd_value("MemorySpdPtr01", 4, old->MemorySpdPtr01,
|
||||
new->MemorySpdPtr01);
|
||||
fsp_display_upd_value("MemorySpdPtr10", 4, old->MemorySpdPtr10,
|
||||
new->MemorySpdPtr10);
|
||||
fsp_display_upd_value("MemorySpdPtr11", 4, old->MemorySpdPtr11,
|
||||
new->MemorySpdPtr11);
|
||||
fsp_display_upd_value("MemorySpdDataLen", 2, old->MemorySpdDataLen,
|
||||
new->MemorySpdDataLen);
|
||||
fsp_display_upd_value("DqByteMapCh0[0]", 1, old->DqByteMapCh0[0],
|
||||
new->DqByteMapCh0[0]);
|
||||
fsp_display_upd_value("DqByteMapCh0[1]", 1, old->DqByteMapCh0[1],
|
||||
new->DqByteMapCh0[1]);
|
||||
fsp_display_upd_value("DqByteMapCh0[2]", 1, old->DqByteMapCh0[2],
|
||||
new->DqByteMapCh0[2]);
|
||||
fsp_display_upd_value("DqByteMapCh0[3]", 1, old->DqByteMapCh0[3],
|
||||
new->DqByteMapCh0[3]);
|
||||
fsp_display_upd_value("DqByteMapCh0[4]", 1, old->DqByteMapCh0[4],
|
||||
new->DqByteMapCh0[4]);
|
||||
fsp_display_upd_value("DqByteMapCh0[5]", 1, old->DqByteMapCh0[5],
|
||||
new->DqByteMapCh0[5]);
|
||||
fsp_display_upd_value("DqByteMapCh0[6]", 1, old->DqByteMapCh0[6],
|
||||
new->DqByteMapCh0[6]);
|
||||
fsp_display_upd_value("DqByteMapCh0[7]", 1, old->DqByteMapCh0[7],
|
||||
new->DqByteMapCh0[7]);
|
||||
fsp_display_upd_value("DqByteMapCh0[8]", 1, old->DqByteMapCh0[8],
|
||||
new->DqByteMapCh0[8]);
|
||||
fsp_display_upd_value("DqByteMapCh0[9]", 1, old->DqByteMapCh0[9],
|
||||
new->DqByteMapCh0[9]);
|
||||
fsp_display_upd_value("DqByteMapCh0[10]", 1, old->DqByteMapCh0[10],
|
||||
new->DqByteMapCh0[10]);
|
||||
fsp_display_upd_value("DqByteMapCh0[11]", 1, old->DqByteMapCh0[11],
|
||||
new->DqByteMapCh0[11]);
|
||||
fsp_display_upd_value("DqByteMapCh1[0]", 1, old->DqByteMapCh1[0],
|
||||
new->DqByteMapCh1[0]);
|
||||
fsp_display_upd_value("DqByteMapCh1[1]", 1, old->DqByteMapCh1[1],
|
||||
new->DqByteMapCh1[1]);
|
||||
fsp_display_upd_value("DqByteMapCh1[2]", 1, old->DqByteMapCh1[2],
|
||||
new->DqByteMapCh1[2]);
|
||||
fsp_display_upd_value("DqByteMapCh1[3]", 1, old->DqByteMapCh1[3],
|
||||
new->DqByteMapCh1[3]);
|
||||
fsp_display_upd_value("DqByteMapCh1[4]", 1, old->DqByteMapCh1[4],
|
||||
new->DqByteMapCh1[4]);
|
||||
fsp_display_upd_value("DqByteMapCh1[5]", 1, old->DqByteMapCh1[5],
|
||||
new->DqByteMapCh1[5]);
|
||||
fsp_display_upd_value("DqByteMapCh1[6]", 1, old->DqByteMapCh1[6],
|
||||
new->DqByteMapCh1[6]);
|
||||
fsp_display_upd_value("DqByteMapCh1[7]", 1, old->DqByteMapCh1[7],
|
||||
new->DqByteMapCh1[7]);
|
||||
fsp_display_upd_value("DqByteMapCh1[8]", 1, old->DqByteMapCh1[8],
|
||||
new->DqByteMapCh1[8]);
|
||||
fsp_display_upd_value("DqByteMapCh1[9]", 1, old->DqByteMapCh1[9],
|
||||
new->DqByteMapCh1[9]);
|
||||
fsp_display_upd_value("DqByteMapCh1[10]", 1, old->DqByteMapCh1[10],
|
||||
new->DqByteMapCh1[10]);
|
||||
fsp_display_upd_value("DqByteMapCh1[11]", 1, old->DqByteMapCh1[11],
|
||||
new->DqByteMapCh1[11]);
|
||||
fsp_display_upd_value("DqsMapCpu2DramCh0[0]", 1,
|
||||
old->DqsMapCpu2DramCh0[0], new->DqsMapCpu2DramCh0[0]);
|
||||
fsp_display_upd_value("DqsMapCpu2DramCh0[1]", 1,
|
||||
old->DqsMapCpu2DramCh0[1], new->DqsMapCpu2DramCh0[1]);
|
||||
fsp_display_upd_value("DqsMapCpu2DramCh0[2]", 1,
|
||||
old->DqsMapCpu2DramCh0[2], new->DqsMapCpu2DramCh0[2]);
|
||||
fsp_display_upd_value("DqsMapCpu2DramCh0[3]", 1,
|
||||
old->DqsMapCpu2DramCh0[3], new->DqsMapCpu2DramCh0[3]);
|
||||
fsp_display_upd_value("DqsMapCpu2DramCh0[4]", 1,
|
||||
old->DqsMapCpu2DramCh0[4], new->DqsMapCpu2DramCh0[4]);
|
||||
fsp_display_upd_value("DqsMapCpu2DramCh0[5]", 1,
|
||||
old->DqsMapCpu2DramCh0[5], new->DqsMapCpu2DramCh0[5]);
|
||||
fsp_display_upd_value("DqsMapCpu2DramCh0[6]", 1,
|
||||
old->DqsMapCpu2DramCh0[6], new->DqsMapCpu2DramCh0[6]);
|
||||
fsp_display_upd_value("DqsMapCpu2DramCh0[7]", 1,
|
||||
old->DqsMapCpu2DramCh0[7], new->DqsMapCpu2DramCh0[7]);
|
||||
fsp_display_upd_value("DqsMapCpu2DramCh1[0]", 1,
|
||||
old->DqsMapCpu2DramCh1[0], new->DqsMapCpu2DramCh1[0]);
|
||||
fsp_display_upd_value("DqsMapCpu2DramCh1[1]", 1,
|
||||
old->DqsMapCpu2DramCh1[1], new->DqsMapCpu2DramCh1[1]);
|
||||
fsp_display_upd_value("DqsMapCpu2DramCh1[2]", 1,
|
||||
old->DqsMapCpu2DramCh1[2], new->DqsMapCpu2DramCh1[2]);
|
||||
fsp_display_upd_value("DqsMapCpu2DramCh1[3]", 1,
|
||||
old->DqsMapCpu2DramCh1[3], new->DqsMapCpu2DramCh1[3]);
|
||||
fsp_display_upd_value("DqsMapCpu2DramCh1[4]", 1,
|
||||
old->DqsMapCpu2DramCh1[4], new->DqsMapCpu2DramCh1[4]);
|
||||
fsp_display_upd_value("DqsMapCpu2DramCh1[5]", 1,
|
||||
old->DqsMapCpu2DramCh1[5], new->DqsMapCpu2DramCh1[5]);
|
||||
fsp_display_upd_value("DqsMapCpu2DramCh1[6]", 1,
|
||||
old->DqsMapCpu2DramCh1[6], new->DqsMapCpu2DramCh1[6]);
|
||||
fsp_display_upd_value("DqsMapCpu2DramCh1[7]", 1,
|
||||
old->DqsMapCpu2DramCh1[7], new->DqsMapCpu2DramCh1[7]);
|
||||
fsp_display_upd_value("DqPinsInterleaved", 1,
|
||||
old->DqPinsInterleaved, new->DqPinsInterleaved);
|
||||
fsp_display_upd_value("RcompResistor[0]", 2, old->RcompResistor[0],
|
||||
new->RcompResistor[0]);
|
||||
fsp_display_upd_value("RcompResistor[1]", 2, old->RcompResistor[1],
|
||||
new->RcompResistor[1]);
|
||||
fsp_display_upd_value("RcompResistor[2]", 2, old->RcompResistor[2],
|
||||
new->RcompResistor[2]);
|
||||
fsp_display_upd_value("RcompTarget[0]", 1, old->RcompTarget[0],
|
||||
new->RcompTarget[0]);
|
||||
fsp_display_upd_value("RcompTarget[1]", 1, old->RcompTarget[1],
|
||||
new->RcompTarget[1]);
|
||||
fsp_display_upd_value("RcompTarget[2]", 1, old->RcompTarget[2],
|
||||
new->RcompTarget[2]);
|
||||
fsp_display_upd_value("RcompTarget[3]", 1, old->RcompTarget[3],
|
||||
new->RcompTarget[3]);
|
||||
fsp_display_upd_value("RcompTarget[4]", 1, old->RcompTarget[4],
|
||||
new->RcompTarget[4]);
|
||||
fsp_display_upd_value("CaVrefConfig", 1, old->CaVrefConfig,
|
||||
new->CaVrefConfig);
|
||||
fsp_display_upd_value("SmramMask", 1, old->SmramMask, new->SmramMask);
|
||||
fsp_display_upd_value("MrcFastBoot", 1, old->MrcFastBoot,
|
||||
new->MrcFastBoot);
|
||||
fsp_display_upd_value("IedSize", 4, old->IedSize, new->IedSize);
|
||||
fsp_display_upd_value("TsegSize", 4, old->TsegSize, new->TsegSize);
|
||||
fsp_display_upd_value("MmioSize", 2, old->MmioSize, new->MmioSize);
|
||||
fsp_display_upd_value("EnableTraceHub", 1, old->EnableTraceHub,
|
||||
new->EnableTraceHub);
|
||||
fsp_display_upd_value("IgdDvmt50PreAlloc", 1, old->IgdDvmt50PreAlloc,
|
||||
new->IgdDvmt50PreAlloc);
|
||||
fsp_display_upd_value("InternalGfx", 1, old->InternalGfx,
|
||||
new->InternalGfx);
|
||||
fsp_display_upd_value("ApertureSize", 1, old->ApertureSize,
|
||||
new->ApertureSize);
|
||||
fsp_display_upd_value("SaGv", 1, old->SaGv, new->SaGv);
|
||||
fsp_display_upd_value("RMT", 1, old->RMT, new->RMT);
|
||||
fsp_display_upd_value("FspCarBase", 1, old->FspCarBase,
|
||||
new->FspCarBase);
|
||||
fsp_display_upd_value("FspCarSize", 1, old->FspCarSize,
|
||||
new->FspCarSize);
|
||||
}
|
||||
|
||||
/* SOC initialization after RAM is enabled. */
|
||||
void soc_after_ram_init(struct romstage_params *params)
|
||||
{
|
||||
/* Set the DISB as soon as possible after DRAM
|
||||
* init and MRC cache is saved.
|
||||
*/
|
||||
pmc_set_disb();
|
||||
}
|
||||
|
||||
struct chipset_power_state *fill_power_state(void)
|
||||
{
|
||||
struct chipset_power_state *ps;
|
||||
|
||||
ps = pmc_get_power_state();
|
||||
pmc_fill_power_state(ps);
|
||||
|
||||
return ps;
|
||||
}
|
||||
|
|
@ -48,20 +48,6 @@ static const struct vr_config default_configs[NUM_VR_DOMAINS] = {
|
|||
.icc_max = VR_CFG_AMP(34),
|
||||
.voltage_limit = 1520,
|
||||
},
|
||||
#if CONFIG(PLATFORM_USES_FSP1_1)
|
||||
[VR_RING] = {
|
||||
.vr_config_enable = 1,
|
||||
.psi1threshold = VR_CFG_AMP(20),
|
||||
.psi2threshold = VR_CFG_AMP(5),
|
||||
.psi3threshold = VR_CFG_AMP(1),
|
||||
.psi3enable = 0,
|
||||
.psi4enable = 0,
|
||||
.imon_slope = 0x0,
|
||||
.imon_offset = 0x0,
|
||||
.icc_max = VR_CFG_AMP(34),
|
||||
.voltage_limit = 1520,
|
||||
},
|
||||
#endif
|
||||
[VR_GT_UNSLICED] = {
|
||||
.vr_config_enable = 1,
|
||||
.psi1threshold = VR_CFG_AMP(20),
|
||||
|
|
@ -246,7 +232,6 @@ static uint16_t get_sku_icc_max(int domain)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#if CONFIG(PLATFORM_USES_FSP2_0)
|
||||
static uint16_t get_sku_ac_dc_loadline(const int domain)
|
||||
{
|
||||
static uint16_t mch_id = 0, igd_id = 0;
|
||||
|
|
@ -316,7 +301,6 @@ static uint16_t get_sku_ac_dc_loadline(const int domain)
|
|||
}
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
void fill_vr_domain_config(void *params,
|
||||
int domain, const struct vr_config *chip_cfg)
|
||||
|
|
@ -348,7 +332,6 @@ void fill_vr_domain_config(void *params,
|
|||
vr_params->IccMax[domain] = get_sku_icc_max(domain);
|
||||
vr_params->VrVoltageLimit[domain] = cfg->voltage_limit;
|
||||
|
||||
#if CONFIG(PLATFORM_USES_FSP2_0)
|
||||
if (cfg->ac_loadline)
|
||||
vr_params->AcLoadline[domain] = cfg->ac_loadline;
|
||||
else
|
||||
|
|
@ -357,5 +340,4 @@ void fill_vr_domain_config(void *params,
|
|||
vr_params->DcLoadline[domain] = cfg->dc_loadline;
|
||||
else
|
||||
vr_params->DcLoadline[domain] = get_sku_ac_dc_loadline(domain);
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue