model_2065x: Use common i945-ivy TSEG SMM init.
Change-Id: I0302cbaeb45a55a4cfee94692eb7372f2b6b206d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10468 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Vladimir Serbinenko
parent
bbd2647b38
commit
0f9aa1c9cd
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@ -7,7 +7,7 @@ subdirs-y += ../../x86/tsc
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subdirs-y += ../../intel/turbo
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subdirs-y += ../../intel/microcode
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subdirs-y += ../../x86/smm
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subdirs-y += ../smm/gen1
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ramstage-y += tsc_freq.c
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romstage-y += tsc_freq.c
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@ -20,5 +20,3 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
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cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
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cpu_incs += $(src)/cpu/intel/model_2065x/cache_as_ram.inc
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
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@ -35,6 +35,7 @@
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#include <pc80/mc146818rtc.h>
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#include "model_2065x.h"
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#include "chip.h"
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#include <cpu/intel/smm/gen1/smi.h>
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/*
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* List of supported C-states in this processor
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@ -113,6 +114,28 @@ static acpi_cstate_t cstate_map[] = {
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{ 0 }
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};
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int cpu_get_apic_id_map(int *apic_id_map)
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{
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int i;
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struct cpuid_result result;
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unsigned threads_per_package, threads_per_core;
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/* Logical processors (threads) per core */
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result = cpuid_ext(0xb, 0);
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threads_per_core = result.ebx & 0xffff;
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/* Logical processors (threads) per package */
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result = cpuid_ext(0xb, 1);
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threads_per_package = result.ebx & 0xffff;
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for (i = 0; i < threads_per_package && i < CONFIG_MAX_CPUS; ++i) {
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apic_id_map[i] = (i % threads_per_core)
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+ ((i / threads_per_core) << 2);
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}
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return threads_per_package;
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}
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static void enable_vmx(void)
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{
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struct cpuid_result regs;
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@ -1,293 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 ChromeOS Authors
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#define __SIMPLE_DEVICE__
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#include <types.h>
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#include <string.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#include <console/console.h>
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#include <northbridge/intel/nehalem/nehalem.h>
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#include <southbridge/intel/ibexpeak/pch.h>
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#include "model_2065x.h"
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#define CORE_THREAD_COUNT_MSR 0x35
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#define SMRR_SUPPORTED (1<<11)
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struct smm_relocation_params {
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u32 smram_base;
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u32 smram_size;
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u32 ied_base;
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u32 ied_size;
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msr_t smrr_base;
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msr_t smrr_mask;
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};
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/* This gets filled in and used during relocation. */
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static struct smm_relocation_params smm_reloc_params;
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static inline void write_smrr(struct smm_relocation_params *relo_params)
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{
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printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
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relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
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wrmsr(SMRRphysBase_MSR, relo_params->smrr_base);
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wrmsr(SMRRphysMask_MSR, relo_params->smrr_mask);
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}
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/* The relocation work is actually performed in SMM context, but the code
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* resides in the ramstage module. This occurs by trampolining from the default
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* SMRAM entry point to here. */
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static void asmlinkage cpu_smm_do_relocation(void *arg)
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{
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em64t101_smm_state_save_area_t *save_state;
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msr_t mtrr_cap;
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struct smm_relocation_params *relo_params;
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const struct smm_module_params *p;
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const struct smm_runtime *runtime;
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int cpu;
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p = arg;
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runtime = p->runtime;
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relo_params = p->arg;
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cpu = p->cpu;
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if (cpu >= CONFIG_MAX_CPUS) {
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printk(BIOS_CRIT,
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"Invalid CPU number assigned in SMM stub: %d\n", cpu);
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return;
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}
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printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu);
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/* All threads need to set IEDBASE and SMBASE in the save state area.
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* Since one thread runs at a time during the relocation the save state
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* is the same for all cpus. */
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save_state = (void *)(runtime->smbase + SMM_DEFAULT_SIZE -
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runtime->save_state_size);
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/* The relocated handler runs with all CPUs concurrently. Therefore
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* stagger the entry points adjusting SMBASE downwards by save state
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* size * CPU num. */
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save_state->smbase = relo_params->smram_base -
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cpu * runtime->save_state_size;
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save_state->iedbase = relo_params->ied_base;
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printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x @ %p\n",
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save_state->smbase, save_state->iedbase, save_state);
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/* Write EMRR and SMRR MSRs based on indicated support. */
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mtrr_cap = rdmsr(MTRRcap_MSR);
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if (mtrr_cap.lo & SMRR_SUPPORTED)
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write_smrr(relo_params);
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southbridge_clear_smi_status();
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}
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static void fill_in_relocation_params(struct smm_relocation_params *params)
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{
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u32 tseg_size;
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u32 tsegmb;
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u32 bgsm;
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int phys_bits;
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/* All range registers are aligned to 4KiB */
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const u32 rmask = ~((1 << 12) - 1);
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/* Some of the range registers are dependent on the number of physical
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* address bits supported. */
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phys_bits = cpuid_eax(0x80000008) & 0xff;
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/* The range bounded by the TSEGMB and BGSM registers encompasses the
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* SMRAM range as well as the IED range. However, the SMRAM available
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* to the handler is 4MiB since the IEDRAM lives TSEGMB + 4MiB.
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*/
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tsegmb = pci_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1;
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bgsm = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_GTT_BASE);
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tseg_size = bgsm - tsegmb;
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params->smram_base = tsegmb;
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params->smram_size = 4 << 20;
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params->ied_base = tsegmb + params->smram_size;
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params->ied_size = tseg_size - params->smram_size;
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/* SMRR has 32-bits of valid address aligned to 4KiB. */
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params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
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params->smrr_base.hi = 0;
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params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRRphysMaskValid;
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params->smrr_mask.hi = 0;
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}
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static void make_apicid_map(int threads_per_package, int threads_per_core, struct smm_loader_params *relo_params)
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{
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int i;
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for (i = 0; i < threads_per_package; ++i) {
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relo_params->runtime->apic_id_to_cpu[i] = (i % threads_per_core)
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+ ((i / threads_per_core) << 2);
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}
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}
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static int install_relocation_handler(int threads_per_package, int threads_per_core,
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struct smm_relocation_params *relo_params)
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{
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/* The default SMM entry happens serially at the default location.
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* Therefore, there is only 1 concurrent save state area. Set the
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* stack size to the save state size, and call into the
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* do_relocation handler. */
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int save_state_size = sizeof(em64t101_smm_state_save_area_t);
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struct smm_loader_params smm_params = {
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.per_cpu_stack_size = save_state_size,
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.num_concurrent_stacks = threads_per_package,
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.per_cpu_save_state_size = save_state_size,
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.num_concurrent_save_states = 1,
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.handler = &cpu_smm_do_relocation,
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.handler_arg = (void *)relo_params,
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};
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if (smm_setup_relocation_handler(&smm_params))
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return -1;
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make_apicid_map(threads_per_package, threads_per_core, &smm_params);
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return 0;
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}
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static void setup_ied_area(struct smm_relocation_params *params)
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{
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char *ied_base;
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struct ied_header ied = {
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.signature = "INTEL RSVD",
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.size = params->ied_size,
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.reserved = {0},
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};
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ied_base = (void *)params->ied_base;
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/* Place IED header at IEDBASE. */
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memcpy(ied_base, &ied, sizeof(ied));
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/* Zero out 32KiB at IEDBASE + 1MiB */
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memset(ied_base + (1 << 20), 0, (32 << 10));
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}
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static int install_permanent_handler(int threads_per_package, int threads_per_core,
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struct smm_relocation_params *relo_params)
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{
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/* There are threads_per_package concurrent stacks and threads_per_package concurrent save
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* state areas. Lastly, set the stack size to the save state size. */
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int save_state_size = sizeof(em64t101_smm_state_save_area_t);
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struct smm_loader_params smm_params = {
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.per_cpu_stack_size = save_state_size,
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.num_concurrent_stacks = threads_per_package,
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.per_cpu_save_state_size = save_state_size,
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.num_concurrent_save_states = threads_per_package,
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};
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printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n",
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relo_params->smram_base);
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if (smm_load_module((void *)relo_params->smram_base,
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relo_params->smram_size, &smm_params))
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return -1;
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make_apicid_map(threads_per_package, threads_per_core, &smm_params);
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return 0;
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}
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static int cpu_smm_setup(void)
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{
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device_t qpdev = PCI_DEV(QUICKPATH_BUS, 0, 1);
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struct cpuid_result result;
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unsigned threads_per_package, threads_per_core;
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/* Logical processors (threads) per core */
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result = cpuid_ext(0xb, 0);
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threads_per_core = result.ebx & 0xffff;
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/* Logical processors (threads) per package */
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result = cpuid_ext(0xb, 1);
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threads_per_package = result.ebx & 0xffff;
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printk(BIOS_DEBUG, "Setting up SMI for CPU\n");
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/* enable the SMM memory window */
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pci_write_config8(qpdev, QPD0F1_SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG);
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fill_in_relocation_params(&smm_reloc_params);
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setup_ied_area(&smm_reloc_params);
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if (threads_per_package > CONFIG_MAX_CPUS) {
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printk(BIOS_CRIT,
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"Error: Hardware CPUs (%d) > MAX_CPUS (%d)\n",
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threads_per_package, CONFIG_MAX_CPUS);
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}
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if (install_relocation_handler(threads_per_package, threads_per_core, &smm_reloc_params)) {
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printk(BIOS_CRIT, "SMM Relocation handler install failed.\n");
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return -1;
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}
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if (install_permanent_handler(threads_per_package, threads_per_core, &smm_reloc_params)) {
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printk(BIOS_CRIT, "SMM Permanent handler install failed.\n");
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return -1;
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}
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/* Ensure the SMM handlers hit DRAM before performing first SMI. */
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/* TODO(adurbin): Is this really needed? */
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wbinvd();
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/* close the SMM memory window and enable normal SMM */
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pci_write_config8(qpdev, QPD0F1_SMRAM, G_SMRAME | C_BASE_SEG);
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return 0;
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}
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void smm_init(void)
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{
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/* Return early if CPU SMM setup failed. */
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if (cpu_smm_setup())
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return;
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southbridge_smm_init();
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/* Initiate first SMI to kick off SMM-context relocation. Note: this
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* SMI being triggered here queues up an SMI in the APs which are in
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* wait-for-SIPI state. Once an AP gets an SIPI it will service the SMI
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* at the SMM_DEFAULT_BASE before jumping to startup vector. */
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southbridge_trigger_smi();
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printk(BIOS_DEBUG, "Relocation complete.\n");
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/* Lock down the SMRAM space. */
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smm_lock();
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}
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void smm_lock(void)
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{
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/* LOCK the SMM memory window and enable normal SMM.
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* After running this function, only a full reset can
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* make the SMM registers writable again.
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*/
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printk(BIOS_DEBUG, "Locking SMM.\n");
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pci_write_config8(PCI_DEV(QUICKPATH_BUS, 0, 1), QPD0F1_SMRAM,
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D_LCK | G_SMRAME | C_BASE_SEG);
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}
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@ -21,6 +21,7 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_NEHALEM),y)
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ramstage-y += ram_calc.c
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ramstage-y += northbridge.c
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ramstage-y += smi.c
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ramstage-y += gma.c
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ramstage-y += acpi.c
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@ -481,11 +481,6 @@ void init_iommu(void);
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#define LAC 0x87 /* Legacy Access Control */
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#define QPD0F1_SMRAM 0x4d /* System Management RAM Control */
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#define D_OPEN (1 << 6)
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#define D_CLS (1 << 5)
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#define D_LCK (1 << 4)
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#define G_SMRAME (1 << 3)
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#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
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#define SKPAD 0xdc /* Scratchpad Data */
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@ -583,12 +578,6 @@ void init_iommu(void);
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#ifndef __ASSEMBLER__
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static inline void barrier(void) { asm("" ::: "memory"); }
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struct ied_header {
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char signature[10];
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u32 size;
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u8 reserved[34];
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} __attribute__ ((packed));
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#define PCI_DEVICE_ID_SB 0x0104
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#define PCI_DEVICE_ID_IB 0x0154
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@ -37,6 +37,7 @@
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#include <cbmem.h>
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#include "chip.h"
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#include "nehalem.h"
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#include <cpu/intel/smm/gen1/smi.h>
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static int bridge_revision_id = -1;
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@ -165,6 +166,18 @@ static void mc_read_resources(device_t dev)
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add_fixed_resources(dev, 10);
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}
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void
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northbridge_get_tseg_base_and_size(u32 *tsegmb, u32 *tseg_size)
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{
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device_t dev;
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u32 bgsm;
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dev = dev_find_slot(0, PCI_DEVFN(0, 0));
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*tsegmb = pci_read_config32(dev, TSEG) & ~1;
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bgsm = pci_read_config32(dev, D0F0_GTT_BASE);
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*tseg_size = bgsm - *tsegmb;
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}
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static void mc_set_resources(device_t dev)
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{
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/* And call the normal set_resources */
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@ -0,0 +1,14 @@
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#define __SIMPLE_DEVICE__
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#include <types.h>
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#include <string.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include "nehalem.h"
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#include <cpu/intel/smm/gen1/smi.h>
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void northbridge_write_smram(u8 smram)
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{
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pcie_write_config8(PCI_DEV(QUICKPATH_BUS, 0, 1), QPD0F1_SMRAM, smram);
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}
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@ -67,11 +67,6 @@ void intel_pch_finalize_smm(void);
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#include "chip.h"
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void pch_enable(device_t dev);
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#endif
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/* These helpers are for performing SMM relocation. */
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void southbridge_smm_init(void);
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void southbridge_trigger_smi(void);
|
||||
void southbridge_clear_smi_status(void);
|
||||
|
||||
int pch_silicon_revision(void);
|
||||
int pch_silicon_type(void);
|
||||
int pch_silicon_supported(int type, int rev);
|
||||
|
|
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|||
|
|
@ -28,6 +28,7 @@
|
|||
#include <cpu/x86/cache.h>
|
||||
#include <cpu/x86/smm.h>
|
||||
#include <string.h>
|
||||
#include <cpu/intel/smm/gen1/smi.h>
|
||||
#include "pch.h"
|
||||
|
||||
/* While we read PMBASE dynamically in case it changed, let's
|
||||
|
|
|
|||
Loading…
Reference in New Issue