mb/google/brya/var/agah: update gpio override
Configure GPIOs according to schematics BUG=b:210970640 TEST=emerge-brya coreboot Change-Id: Icfd1e09761e51aca9c23f3ab340adac7a66a3ada Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Tony Huang
Felix Held
parent
80a7f4e7b6
commit
0f9c7c009f
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# SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += gpio.c
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romstage-y += gpio.c
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ramstage-y += gpio.c
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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#include <soc/gpio.h>
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/* Pad configuration in ramstage */
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static const struct pad_config override_gpio_table[] = {
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/* A7 : SRCCLK_OE7# ==> LAN_WAKE_ODL */
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PAD_CFG_GPI_SCI_LOW(GPP_A7, NONE, DEEP, EDGE_SINGLE),
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/* A8 : SRCCLKREQ7# ==> USB2_A2_RT_RST_ODL */
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PAD_CFG_GPO(GPP_A8, 1, DEEP),
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/* A12 : SATAXPCIE1 ==> EN_PP3300_LAN_X */
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PAD_CFG_GPO(GPP_A12, 1, DEEP),
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/* A14 : USB_OC1# ==> USB_C0_OC_ODL */
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PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
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/* A15 : USB_OC2# ==> USB_C2_OC_ODL */
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PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
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/* A17 : DISP_MISCC ==> EN_GPU_PPVAR_GPU_NVVDD_X_PCH */
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PAD_CFG_GPO(GPP_A17, 1, DEEP),
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/* A19 : DDSP_HPD1 ==> EN_PCH_PPVAR_GPU_FBVDDQ_X_L */
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PAD_CFG_GPO(GPP_A19, 0, DEEP),
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/* A20 : DDSP_HPD2 ==> NC */
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PAD_NC(GPP_A20, NONE),
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/* A21 : DDPC_CTRCLK ==> EN_PP3300_GPU_X */
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PAD_CFG_GPO(GPP_A21, 0, DEEP),
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/* A22 : DDPC_CTRCLK ==> PG_PP3300_GPU_X_OD */
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PAD_CFG_GPI(GPP_A22, NONE, DEEP),
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/* B3 : PROC_GP2 ==> GPU_PERST_L */
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PAD_CFG_GPO(GPP_B3, 1, DEEP),
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/* B5 : ISH_I2C0_SDA ==> PCH_I2C_NVDD_GPU_SDA */
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PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),
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/* B6 : ISH_I2C0_SDA ==> PCH_I2C_NVDD_GPU_SCL */
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PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),
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/* B15 : TIME_SYNC0 ==> NC */
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PAD_NC(GPP_B15, NONE),
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/* C0 : SMBCLK ==> NC */
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PAD_NC(GPP_C0, NONE),
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/* C1 : SMBDATA ==> NC */
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PAD_NC(GPP_C1, NONE),
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/* C3 : SML0CLK ==> NC */
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PAD_NC(GPP_C3, NONE),
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/* C4 : SML0DATA ==> NC */
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PAD_NC(GPP_C4, NONE),
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/* C6 : SML1CLK ==> NC */
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PAD_NC(GPP_C6, NONE),
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/* C7 : SML1DATA ==> NC */
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PAD_NC(GPP_C7, NONE),
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/* D0 : ISH_GP0 ==> NC */
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PAD_NC(GPP_D0, NONE),
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/* D1 : ISH_GP1 ==> NC */
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PAD_NC(GPP_D1, NONE),
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/* D2 : ISH_GP2 ==> LAN_PR_ISOLATE_ODL */
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PAD_CFG_GPO(GPP_D2, 1, DEEP),
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/* D3 : ISH_GP3 ==> NC */
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PAD_NC(GPP_D3, NONE),
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/* D5 : SRCCLKREQ0# ==> GPU_CLKREQ_ODL */
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PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
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/* D9 : ISH_SPI_CS# ==> GPU_THERM_INT_ODL */
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PAD_CFG_GPI(GPP_D9, NONE, DEEP),
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/* D10 : ISH_SPI_CLK ==> GPP_D10_STRAP */
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PAD_NC(GPP_D10, NONE),
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/* D13 : ISH_UART0_RXD ==> NC */
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PAD_NC(GPP_D13, NONE),
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/* D15 : ISH_UART0_RTS# ==> NC */
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PAD_NC(GPP_D15, NONE),
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/* D16 : ISH_UART0_CTS# ==> NC */
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PAD_NC(GPP_D16, NONE),
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/* E0 : SATAXPCIE0 ==> EN_PPVAR_GPU_NVVDD_X_OD */
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PAD_CFG_GPO(GPP_E0, 0, DEEP),
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/* E3 : PROC_GP0 ==> NC */
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PAD_NC(GPP_E3, NONE),
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/* E4 : SATA_DEVSLP0 ==> PG_PPVAR_GPU_FBVDDQ_X_OD */
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PAD_CFG_GPO(GPP_E4, 0, DEEP),
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/* E5 : SATA_DEVSLP1 ==> PG_GPU_ALLRAILS */
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PAD_CFG_GPI(GPP_E5, NONE, DEEP),
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/* E7 : PROC_GP1 ==> NC */
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PAD_NC(GPP_E7, NONE),
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/* E9 : USB_OC0# ==> USB_A2_OC_ODL */
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PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
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/* E10 : THC0_SPI1_CS# ==> EN_PP0950_GPU_X */
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PAD_CFG_GPO(GPP_E10, 0, DEEP),
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/* E16 : RSVD_TP ==> PG_PPVAR_GPU_NVVDD_X_OD */
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PAD_CFG_GPO(GPP_E16, 0, DEEP),
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/* E17 : RSVD_TP ==> PG_PP0950_GPU_X_OD */
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PAD_CFG_GPI(GPP_E17, NONE, DEEP),
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/* E18 : DDP1_CTRLCLK ==> EN_PP1800_GPU_X */
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PAD_CFG_GPO(GPP_E18, 0, DEEP),
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/* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */
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PAD_NC(GPP_E19, NONE),
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/* E20 : DDP2_CTRLCLK ==> PG_PP1800_GPU_X_OD */
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PAD_CFG_GPI(GPP_E20, NONE, DEEP),
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/* E21 : DDP2_CTRLDATA ==> GPP_E21_STRAP */
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PAD_NC(GPP_E21, NONE),
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/* F6 : CNV_PA_BLANKING ==> NC */
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PAD_NC(GPP_F6, NONE),
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/* F11 : THC1_SPI2_CLK ==> NC */
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PAD_NC(GPP_F11, NONE),
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/* F12 : GSXDOUT ==> NC */
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PAD_NC(GPP_F12, NONE),
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/* F13 : GSXDOUT ==> NC */
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PAD_NC(GPP_F13, NONE),
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/* F15 : GSXSRESET# ==> NC */
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PAD_NC(GPP_F15, NONE),
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/* F16 : GSXCLK ==> NC */
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PAD_NC(GPP_F16, NONE),
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/* F19 : SRCCLKREQ6# ==> NC */
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PAD_NC(GPP_F19, NONE),
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/* F20 : EXT_PWR_GATE# ==> NC */
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PAD_NC(GPP_F20, NONE),
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/* F21 : EXT_PWR_GATE2# ==> NC */
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PAD_NC(GPP_F21, NONE),
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/* H6 : I2C1_SDA ==> PCH_I2C_GPU_SDA */
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PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
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/* H7 : I2C1_SCL ==> PCH_I2C_GPU_SCL */
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PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
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/* H8 : I2C4_SDA ==> NC */
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PAD_NC(GPP_H8, NONE),
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/* H9 : I2C4_SCL ==> NC */
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PAD_NC(GPP_H9, NONE),
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/* H19 : SRCCLKREQ4# ==> LAN_CLKREQ_ODL */
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PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
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/* H21 : IMGCLKOUT2 ==> NC */
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PAD_NC(GPP_H21, NONE),
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/* H22 : IMGCLKOUT3 ==> NC */
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PAD_NC(GPP_H22, NONE),
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/* R4 : HDA_RST# ==> DMIC_CLK0 */
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PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),
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/* R5 : HDA_SDI1 ==> DMIC_DATA0 */
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PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
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/* R6 : I2S_PCH_TX_SPKR_RX ==> NC */
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PAD_NC(GPP_R6, NONE),
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/* R7 : I2S_PCH_RX_SPKR_TX ==> NC */
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PAD_NC(GPP_R7, NONE),
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/* S0 : SNDW0_CLK ==> I2S_SPKR_SCLK */
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PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4),
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/* S1 : SNDW0_DATA ==> I2S_SPKR_SFRM */
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PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4),
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/* S2 : SNDW1_CLK ==> I2S_PCH_SPKR_RX */
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PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4),
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/* S3 : SNDW1_DATA ==> I2S_PCH_SPKR_TX */
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PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4),
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/* S6 : SNDW3_CLK ==> SDW_HP_CLK */
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PAD_CFG_NF(GPP_S6, NONE, DEEP, NF1),
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/* S7 : SNDW3_DATA ==> SDW_HP_DATA */
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PAD_CFG_NF(GPP_S7, NONE, DEEP, NF1),
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};
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
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/* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
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PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
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/* B8 : ISH_I2C1_SCL ==> PCH_I2C_TPM_SCL */
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PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
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/* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
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PAD_CFG_GPO(GPP_D11, 1, DEEP),
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/* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
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PAD_CFG_GPI(GPP_E13, NONE, DEEP),
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/* E15 : RSVD_TP ==> PCH_WP_OD */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
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/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
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PAD_CFG_GPI(GPP_F18, NONE, DEEP),
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/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
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PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
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/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
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PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
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/*
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* enable EN_PP3300_SSD in bootblock, then PERST# is asserted, and
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* then deassert PERST# in romstage
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*/
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/* H13 : I2C7_SCL ==> EN_PP3300_SD */
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PAD_CFG_GPO(GPP_H13, 1, DEEP),
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/* B4 : PROC_GP3 ==> SSD_PERST_L */
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PAD_CFG_GPO(GPP_B4, 0, DEEP),
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};
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static const struct pad_config romstage_gpio_table[] = {
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/* B4 : PROC_GP3 ==> SSD_PERST_L */
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PAD_CFG_GPO(GPP_B4, 1, DEEP),
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};
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const struct pad_config *variant_gpio_override_table(size_t *num)
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{
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*num = ARRAY_SIZE(override_gpio_table);
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return override_gpio_table;
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}
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const struct pad_config *variant_early_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(early_gpio_table);
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return early_gpio_table;
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}
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const struct pad_config *variant_romstage_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(romstage_gpio_table);
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return romstage_gpio_table;
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}
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