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intel/kunimitsu: perform early init for CAR *stage 

In order to support both separate verstage and a verified boot after
romstage one needs to ensure the proper GPIO and EC configuration
been complete. Therefore, move that logic to
car_mainboard_post_console_init() in car.c file which gets called
in the early flow of a CAR stage (either verstage or romstage).

BUG=chrome-os-partner:44827
BRANCH=glados
TEST=Built kunimitsu w/ separate verstage.

Change-Id: If34cae5516a6df7f72f1f57cab495db70787177e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 543155665e1b05efe82c7440c124a5c83c656aa6
Original-Change-Id: I7281c4373fcbaaf0beedaa63dcf0dedb5316349f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/324074
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13584
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Aaron Durbin 2016-01-25 17:53:18 -06:00 committed by Patrick Georgi
parent 586a517dfd
commit 0f9d5c454b
3 changed files with 38 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/intel/kunimitsu/Makefile.inc
View File

@ -17,6 +17,7 @@
subdirs-y += spd
romstage-y += boardid.c
romstage-y += car.c
romstage-y += pei_data.c
verstage-$(CONFIG_CHROMEOS) += chromeos.c
@ -31,3 +32,5 @@ ramstage-y += pei_data.c
ramstage-y += ramstage.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
verstage-y += car.c

35
src/mainboard/intel/kunimitsu/car.c Normal file
View File

@ -0,0 +1,35 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <ec/google/chromeec/ec.h>
#include <fsp/car.h>
#include <soc/gpio.h>
#include "gpio.h"
static void early_config_gpio(void)
{
/* This is a hack for FSP because it does things in MemoryInit()
* which it shouldn't be. We have to prepare certain gpios here
* because of the brokenness in FSP. */
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
}
void car_mainboard_post_console_init(void)
{
/* Ensure the EC and PD are in the right mode for recovery */
google_chromeec_early_init();
early_config_gpio();
}

16
src/mainboard/intel/kunimitsu/romstage.c
View File

@ -15,10 +15,7 @@
* GNU General Public License for more details.
*/
#include <cbfs.h>
#include <console/console.h>
#include <string.h>
#include <ec/google/chromeec/ec.h>
#include <gpio.h>
#include <soc/pei_data.h>
#include <soc/pei_wrapper.h>
@ -26,14 +23,6 @@
#include "gpio.h"
#include "spd/spd.h"
static void early_config_gpio(void)
{
/* This is a hack for FSP because it does things in MemoryInit()
* which it shouldn't be. We have to prepare certain gpios here
* because of the brokenness in FSP. */
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
}
void mainboard_romstage_entry(struct romstage_params *params)
{
/* PCH_MEM_CFG[3:0] */
@ -44,11 +33,6 @@ void mainboard_romstage_entry(struct romstage_params *params)
GPIO_MEM_CONFIG_3,
};
/* Ensure the EC and PD are in the right mode for recovery */
google_chromeec_early_init();
early_config_gpio();
params->pei_data->mem_cfg_id = gpio_base2_value(spd_gpios,
ARRAY_SIZE(spd_gpios));
/* Fill out PEI DATA */