Hudson: Changes to agesa/hudson FADT for ACPI 3.0
Update the southbridge/amd/agesa/hudson FADT generation for ACPI 3.0 compliance similar to what was done for cimx/SB800/fadt.c in commit9aa4389. commit9aa43892e6Author: Martin Roth <martin@se-eng.com> Date: Fri May 25 12:23:32 2012 -0600 Update SB800 CIMX FADT According to the datasheet, PMA_CNT_BLK is no longer available and PM2_CNT_BLK should not be used. Setup for these has been removed from the table and .h file. Change-Id: Ied8eb1f26b4aa364d051ec5f7ed6f482bb440957 Signed-off-by: Martin Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/2140 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
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Martin Roth
Martin Roth
parent
931df3a96b
commit
0fbaf18ed4
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@ -28,6 +28,16 @@
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#include <device/device.h>
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#include "hudson.h"
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#define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042)
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#ifndef FADT_PM_PROFILE
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#define FADT_PM_PROFILE PM_UNSPECIFIED
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#endif
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/*
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* Reference section 5.2.9 Fixed ACPI Description Table (FADT)
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* in the ACPI 3.0b specification.
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*/
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void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
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{
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acpi_header_t *header = &(fadt->header);
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@ -37,24 +47,23 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
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/* Prepare the header */
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memset((void *)fadt, 0, sizeof(acpi_fadt_t));
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memcpy(header->signature, "FACP", 4);
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header->length = 244;
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header->revision = 3;
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header->length = sizeof(acpi_fadt_t);
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header->revision = ACPI_FADT_REV_ACPI_3_0;
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memcpy(header->oem_id, OEM_ID, 6);
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memcpy(header->oem_table_id, "COREBOOT", 8);
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memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
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memcpy(header->asl_compiler_id, ASLC, 4);
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header->asl_compiler_revision = 0;
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fadt->firmware_ctrl = (u32) facs;
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fadt->dsdt = (u32) dsdt;
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/* 3=Workstation,4=Enterprise Server, 7=Performance Server */
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fadt->preferred_pm_profile = 0x03;
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fadt->sci_int = 9;
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/* disable system management mode by setting to 0: */
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fadt->smi_cmd = 0;
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fadt->acpi_enable = 0xf0;
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fadt->acpi_disable = 0xf1;
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fadt->s4bios_req = 0x0;
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fadt->pstate_cnt = 0xe2;
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fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */
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fadt->preferred_pm_profile = FADT_PM_PROFILE;
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fadt->sci_int = 9; /* HUDSON - IRQ 09 – ACPI SCI */
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fadt->smi_cmd = 0; /* disable system management mode */
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fadt->acpi_enable = 0; /* unused if SMI_CMD = 0 */
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fadt->acpi_disable = 0; /* unused if SMI_CMD = 0 */
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fadt->s4bios_req = 0; /* unused if SMI_CMD = 0 */
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fadt->pstate_cnt = 0; /* unused if SMI_CMD = 0 */
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pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF);
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pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8);
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@ -72,9 +81,6 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
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pm_iowrite(0x6A, 0); /* AcpiSmiCmdLo */
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pm_iowrite(0x6B, 0); /* AcpiSmiCmdHi */
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pm_iowrite(0x6C, ACPI_PMA_CNT_BLK & 0xFF);
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pm_iowrite(0x6D, ACPI_PMA_CNT_BLK >> 8);
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pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses
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* the contents of the PM registers at
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* index 60-6B to decode ACPI I/O address.
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@ -85,100 +91,124 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
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fadt->pm1b_evt_blk = 0x0000;
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fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
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fadt->pm1b_cnt_blk = 0x0000;
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fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
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fadt->pm2_cnt_blk = 0x0000;
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fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
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fadt->gpe0_blk = ACPI_GPE0_BLK;
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fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */
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fadt->gpe1_blk = 0x0000; /* No gpe1 block in hudson */
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fadt->pm1_evt_len = 4;
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fadt->pm1_cnt_len = 2;
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fadt->pm2_cnt_len = 1;
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fadt->pm_tmr_len = 4;
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fadt->gpe0_blk_len = 8;
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fadt->pm1_evt_len = 4; /* 32 bits */
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fadt->pm1_cnt_len = 2; /* 16 bits */
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fadt->pm2_cnt_len = 0;
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fadt->pm_tmr_len = 4; /* 32 bits */
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fadt->gpe0_blk_len = 8; /* 64 bits */
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fadt->gpe1_blk_len = 0;
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fadt->gpe1_base = 0;
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fadt->cst_cnt = 0xe3;
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fadt->p_lvl2_lat = 101;
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fadt->p_lvl3_lat = 1001;
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fadt->flush_size = 0;
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fadt->flush_stride = 0;
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fadt->duty_offset = 1;
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fadt->duty_width = 3;
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fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */
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fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
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fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
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fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */
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fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */
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fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */
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fadt->duty_width = 3; /* CLK_VAL bits 3:1 */
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fadt->day_alrm = 0; /* 0x7d these have to be */
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fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
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fadt->century = 0; /* 0x7f to make rtc alrm work */
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fadt->iapc_boot_arch = 0x3; /* See table 5-11 */
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fadt->flags = 0x0001c1a5 | 1 << 10;/* 0x25; */
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fadt->century = 0; /* 0x7f to make rtc alarm work */
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fadt->iapc_boot_arch = FADT_BOOT_ARCH; /* See table 5-10 */
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fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */
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fadt->flags = ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */
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ACPI_FADT_C1_SUPPORTED |
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ACPI_FADT_SLEEP_BUTTON |
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ACPI_FADT_S4_RTC_WAKE |
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ACPI_FADT_32BIT_TIMER |
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ACPI_FADT_RESET_REGISTER |
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ACPI_FADT_PCI_EXPRESS_WAKE |
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ACPI_FADT_PLATFORM_CLOCK |
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ACPI_FADT_S4_RTC_VALID |
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ACPI_FADT_REMOTE_POWER_ON;
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fadt->res2 = 0;
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fadt->reset_reg.space_id = 1;
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/* Format is from 5.2.3.1: Generic Address Structure */
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/* reset_reg: see section 4.7.3.6 ACPI 3.0a spec */
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/* 8 bit write of value 0x06 to 0xCF9 in IO space */
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fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->reset_reg.bit_width = 8;
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fadt->reset_reg.bit_offset = 0;
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fadt->reset_reg.resv = 0;
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fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
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fadt->reset_reg.addrl = 0xcf9;
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fadt->reset_reg.addrh = 0x0;
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fadt->reset_value = 6;
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fadt->x_firmware_ctl_l = (u32) facs;
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fadt->res3 = 0; /* reserved, MUST be 0 ACPI 3.0 */
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fadt->res4 = 0; /* reserved, MUST be 0 ACPI 3.0 */
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fadt->res5 = 0; /* reserved, MUST be 0 ACPI 3.0 */
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fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */
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fadt->x_firmware_ctl_h = 0;
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fadt->x_dsdt_l = (u32) dsdt;
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fadt->x_dsdt_h = 0;
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fadt->x_pm1a_evt_blk.space_id = 1;
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fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm1a_evt_blk.bit_width = 32;
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fadt->x_pm1a_evt_blk.bit_offset = 0;
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fadt->x_pm1a_evt_blk.resv = 0;
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fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
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fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
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fadt->x_pm1a_evt_blk.addrh = 0x0;
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fadt->x_pm1b_evt_blk.space_id = 1;
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fadt->x_pm1b_evt_blk.bit_width = 4;
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fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm1b_evt_blk.bit_width = 0;
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fadt->x_pm1b_evt_blk.bit_offset = 0;
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fadt->x_pm1b_evt_blk.resv = 0;
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fadt->x_pm1b_evt_blk.access_size = 0;
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fadt->x_pm1b_evt_blk.addrl = 0x0;
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fadt->x_pm1b_evt_blk.addrh = 0x0;
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fadt->x_pm1a_cnt_blk.space_id = 1;
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fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm1a_cnt_blk.bit_width = 16;
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fadt->x_pm1a_cnt_blk.bit_offset = 0;
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fadt->x_pm1a_cnt_blk.resv = 0;
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fadt->x_pm1a_cnt_blk.access_size = 0;
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fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
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fadt->x_pm1a_cnt_blk.addrh = 0x0;
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fadt->x_pm1b_cnt_blk.space_id = 1;
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fadt->x_pm1b_cnt_blk.bit_width = 2;
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fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm1b_cnt_blk.bit_width = 0;
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fadt->x_pm1b_cnt_blk.bit_offset = 0;
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fadt->x_pm1b_cnt_blk.resv = 0;
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fadt->x_pm1b_cnt_blk.access_size = 0;
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fadt->x_pm1b_cnt_blk.addrl = 0x0;
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fadt->x_pm1b_cnt_blk.addrh = 0x0;
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fadt->x_pm2_cnt_blk.space_id = 1;
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/*
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* Note: Under this current AMD C state implementation, this is no longer
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* used and should not be reported to OS.
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*/
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fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm2_cnt_blk.bit_width = 0;
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fadt->x_pm2_cnt_blk.bit_offset = 0;
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fadt->x_pm2_cnt_blk.resv = 0;
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fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
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fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
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fadt->x_pm2_cnt_blk.addrl = 0;
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fadt->x_pm2_cnt_blk.addrh = 0x0;
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fadt->x_pm_tmr_blk.space_id = 1;
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fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm_tmr_blk.bit_width = 32;
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fadt->x_pm_tmr_blk.bit_offset = 0;
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fadt->x_pm_tmr_blk.resv = 0;
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fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
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fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
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fadt->x_pm_tmr_blk.addrh = 0x0;
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fadt->x_gpe0_blk.space_id = 1;
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fadt->x_gpe0_blk.bit_width = 32;
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fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */
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fadt->x_gpe0_blk.bit_offset = 0;
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fadt->x_gpe0_blk.resv = 0;
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fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
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fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
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fadt->x_gpe0_blk.addrh = 0x0;
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fadt->x_gpe1_blk.space_id = 1;
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fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_gpe1_blk.bit_width = 0;
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fadt->x_gpe1_blk.bit_offset = 0;
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fadt->x_gpe1_blk.resv = 0;
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fadt->x_gpe1_blk.access_size = 0;
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fadt->x_gpe1_blk.addrl = 0;
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fadt->x_gpe1_blk.addrh = 0x0;
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@ -35,7 +35,6 @@
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#define ACPI_PM_EVT_BLK (HUDSON_ACPI_IO_BASE + 0x00) /* 4 bytes */
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#define ACPI_PM1_CNT_BLK (HUDSON_ACPI_IO_BASE + 0x04) /* 2 bytes */
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#define ACPI_PMA_CNT_BLK (HUDSON_ACPI_IO_BASE + 0x0F) /* 1 byte, TODO: Is it 0xFE00? */
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#define ACPI_PM_TMR_BLK (HUDSON_ACPI_IO_BASE + 0x18) /* 4 bytes */
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#define ACPI_GPE0_BLK (HUDSON_ACPI_IO_BASE + 0x10) /* 8 bytes */
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#define ACPI_CPU_CONTROL (HUDSON_ACPI_IO_BASE + 0x08) /* 6 bytes */
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@ -55,7 +54,6 @@ void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val);
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#define CPU_CNT_BLK_ADDRESS 0x810 // CpuControlBlkAddr;
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#define GPE0_BLK_ADDRESS 0x820 // AcpiGpe0BlkAddr;
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#define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr;
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#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr;
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#define SPIROM_BASE_ADDRESS_REGISTER 0xA0
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#ifdef __PRE_RAM__
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