soc/intel/icl: drop wrong, unused code

The ids used in function `soc_get_pch_series()` are not valid for
Icelake. Since it's not even used, instead of fixing it, drop it.

Change-Id: I4a1ee4b84f11ea314cb666ce4506ff90168da0ca
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49875
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/icelake/espi.c

@@ -36,24 +36,6 @@ void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)
 	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);
 }
 
-uint8_t get_pch_series(void)
-{
-	uint16_t lpc_did_hi_byte;
-
-	/*
-	 * Fetch upper 8 bits on ESPI device ID to determine PCH type
-	 * Adding 1 to the offset to fetch upper 8 bits
-	 */
-	lpc_did_hi_byte = pci_read_config8(PCH_DEV_ESPI, PCI_DEVICE_ID + 1);
-
-	if (lpc_did_hi_byte == 0x9D)
-		return PCH_LP;
-	else if (lpc_did_hi_byte == 0xA3)
-		return PCH_H;
-	else
-		return PCH_UNKNOWN_SERIES;
-}
-
 #if ENV_RAMSTAGE
 static void soc_mirror_dmi_pcr_io_dec(void)
 {

src/soc/intel/icelake/include/soc/espi.h

@@ -26,15 +26,4 @@
 #define PCCTL			0xE0 /* PCI Clock Control */
 #define   CLKRUN_EN		(1 << 0)
 
-/*
- * This function will help to differentiate between 2 PCH on single type of soc.
- * Since same soc may have LP series pch or H series PCH, we need to
- * differentiate by reading upper 8 bits of PCH device ids.
- *
- * Return:
- *	Return PCH_LP or PCH_H macro in case of respective device ID found.
- *	PCH_UNKNOWN_SERIES in case of invalid device ID.
- */
-uint8_t get_pch_series(void);
-
 #endif

src/soc/intel/icelake/include/soc/pch.h

@@ -3,10 +3,6 @@
 #ifndef _SOC_ICELAKE_PCH_H_
 #define _SOC_ICELAKE_PCH_H_
 
-#define PCH_H				1
-#define PCH_LP				2
-#define PCH_UNKNOWN_SERIES		0xFF
-
 #define PCIE_CLK_NOTUSED		0xFF
 #define PCIE_CLK_LAN			0x70
 #define PCIE_CLK_FREE			0x80