soc/amd/common/acp: add acp_gen2
The gen2 ACP register definitions and locations are different from previous models. Specific code is refactored into acp_gen1 and acp_gen2. Update ACP register locations and definitions for gen2. Change-Id: If665b93cddf22435512f1276fcfee2f497dc6ef5 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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@ -3,3 +3,9 @@ config SOC_AMD_COMMON_BLOCK_ACP_GEN1
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help
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help
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Select this option to perform Audio Co-Processor(ACP) configuration.
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Select this option to perform Audio Co-Processor(ACP) configuration.
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Used by the ACP in AMD family 17h, 19h, and earlier (picasso, cezanne)
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Used by the ACP in AMD family 17h, 19h, and earlier (picasso, cezanne)
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config SOC_AMD_COMMON_BLOCK_ACP_GEN2
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bool
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help
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Select this option to perform Audio Co-Processor(ACP) configuration.
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Used by the ACP in AMD sabrina (family 17h) and possibly newer CPUs.
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@ -1,2 +1,5 @@
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ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACP_GEN1) += acp.c
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ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACP_GEN1) += acp.c
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ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACP_GEN1) += acp_gen1.c
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ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACP_GEN1) += acp_gen1.c
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ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACP_GEN2) += acp.c
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ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACP_GEN2) += acp_gen2.c
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@ -12,6 +12,8 @@
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#include <commonlib/helpers.h>
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#include <commonlib/helpers.h>
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#include "acp_def.h"
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#include "acp_def.h"
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_Static_assert(!(CONFIG(SOC_AMD_COMMON_BLOCK_ACP_GEN1) && CONFIG(SOC_AMD_COMMON_BLOCK_ACP_GEN2)),
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"Cannot select both ACP_GEN1 and ACP_GEN2 - check your config");
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static const char *acp_acpi_name(const struct device *dev)
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static const char *acp_acpi_name(const struct device *dev)
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{
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{
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@ -0,0 +1,42 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <amdblocks/acp.h>
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#include <amdblocks/chip.h>
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#include <device/device.h>
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#include <device/mmio.h>
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#include <console/console.h>
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#include "acp_def.h"
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/* ACP registers and associated fields */
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#define ACP_PME_EN 0x41400
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#define PME_EN_MASK (1 << 0)
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#define ACP_I2S_PIN_CONFIG 0x41440 /* HDA, Soundwire, I2S */
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#define PIN_CONFIG_MASK (0xf << 0)
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#define ACP_I2S_WAKE_EN 0x4145C
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#define WAKE_EN_MASK (1 << 0)
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static void acp_update32(uintptr_t bar, uint32_t reg, uint32_t clear, uint32_t set)
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{
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clrsetbits32((void *)(bar + reg), clear, set);
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}
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void acp_init(struct device *dev)
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{
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const struct soc_amd_common_config *cfg = soc_get_common_config();
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struct resource *res;
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uintptr_t bar;
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res = dev->resource_list;
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if (!res || !res->base) {
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printk(BIOS_ERR, "Error, unable to configure pin in %s\n", __func__);
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return;
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}
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/* Set the proper I2S_PIN_CONFIG state */
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bar = (uintptr_t)res->base;
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acp_update32(bar, ACP_I2S_PIN_CONFIG, PIN_CONFIG_MASK, cfg->acp_config.acp_pin_cfg);
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/* Enable ACP_PME_EN and ACP_I2S_WAKE_EN for I2S_WAKE event */
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acp_update32(bar, ACP_I2S_WAKE_EN, WAKE_EN_MASK, !!cfg->acp_config.acp_i2s_wake_enable);
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acp_update32(bar, ACP_PME_EN, PME_EN_MASK, !!cfg->acp_config.acp_pme_enable);
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}
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@ -7,12 +7,29 @@
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struct acp_config {
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struct acp_config {
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enum {
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enum {
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#if CONFIG(SOC_AMD_COMMON_BLOCK_ACP_GEN2)
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ACP_PINS_HDA_3SDI = 1, /* HDA 3xSDI */
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ACP_PINS_HDA_1SDI_1SW = 2, /* HDA 1xSDI, SW w/Data0 */
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ACP_PINS_4SW_1SW = 3, /* SW w/Data0-3, SW w/Data0 */
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ACP_PINS_HDA_3SDI_PDM2 = 4, /* HDA 3xSDI, PDM 2CH */
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ACP_PINS_HDA_1SDI_PDM6 = 5, /* HDA 1xSDI, PDM 6CH */
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ACP_PINS_HDA_1SDI_1SW_PDM2 = 6, /* HDA 1xSDI, SW w/Data0, PDM 2CH */
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ACP_PINS_4SW_PDM6 = 7, /* SW w/Data0-3, PDM 6CH */
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ACP_PINS_4SW_1SW_PDM2 = 8, /* SW w/Data0-3, SW w/Data0, PDM 2CH */
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ACP_PINS_I2S = 9, /* 3xI2S, Refclk, Intr */
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ACP_PINS_HDA_3SDI_PDM6_I2S = 10,/* HDA 3xSDI, PDM 6CH, I2S */
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ACP_PINS_HDA_3SDI_PDM8 = 11, /* HDA 3xSDI, PDM 8CH */
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ACP_PINS_HDA_1SDI_1SW_PDM6_I2S = 12,/* HDA 1xSDI, SW w/Data0, PDM 6CH, I2S */
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ACP_PINS_4SW_1SW_PDM6_I2S = 13, /* SW w/Data0-3, SW w/Data0, PDM 6CH, I2S */
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ACP_PINS_4SW_1SW_PDM8 = 14, /* SW w/Data0-3, SW w/Data0, PDM 8CH */
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#else
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I2S_PINS_MAX_HDA = 0, /* HDA w/reset 3xSDI, SW w/Data0 */
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I2S_PINS_MAX_HDA = 0, /* HDA w/reset 3xSDI, SW w/Data0 */
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I2S_PINS_MAX_MHDA = 1, /* HDA no reset 3xSDI, SW w/Data0-1 */
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I2S_PINS_MAX_MHDA = 1, /* HDA no reset 3xSDI, SW w/Data0-1 */
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I2S_PINS_MIN_HDA = 2, /* HDA w/reset 1xSDI, SW w/Data0-2 */
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I2S_PINS_MIN_HDA = 2, /* HDA w/reset 1xSDI, SW w/Data0-2 */
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I2S_PINS_MIN_MHDA = 3, /* HDA no reset 1xSDI, SW w/Data0-3 */
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I2S_PINS_MIN_MHDA = 3, /* HDA no reset 1xSDI, SW w/Data0-3 */
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I2S_PINS_I2S_TDM = 4,
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I2S_PINS_I2S_TDM = 4,
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I2S_PINS_UNCONF = 7, /* All pads will be input mode */
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I2S_PINS_UNCONF = 7, /* All pads will be input mode */
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#endif
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} acp_pin_cfg;
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} acp_pin_cfg;
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/* Enable ACP I2S wake feature (0 = disable, 1 = enable) */
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/* Enable ACP I2S wake feature (0 = disable, 1 = enable) */
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