libpayload arm64: update mmu translation table granule size, logic and macros
1. change mmu granule size from 64KB to 4KB 2. correct level 1 translation table creation logic 3. automatically calculate granule size related macros BRANCH=none BUG=none TEST=boot to kernel on oak board Change-Id: Ic62c7863dff53f566b82b68ff1d1ad9ec5d0698d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e5de7d942e42a8202fb879ce64b871864b1b9d38 Original-Change-Id: I78d7838921fa82a670e18ddc2de6d766dc7a2146 Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/266010 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Commit-Queue: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: http://review.coreboot.org/10010 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
This commit is contained in:
Jimmy Huang
Patrick Georgi
parent
dea4597bd4
commit
0fd3e79d0d
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@ -200,12 +200,24 @@ static uint64_t init_xlat_table(uint64_t base_addr,
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/*
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* L1 table lookup
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* If VA has bits more than 41, lookup starts at L1
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* If VA has bits more than L2 can resolve, lookup starts at L1
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* Assumption: we don't need L0 table in coreboot
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*/
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if (l1_index) {
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table = get_next_level_table(&table[l1_index]);
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if (!table)
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return 0;
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if (BITS_PER_VA > L1_ADDR_SHIFT) {
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if ((size >= L1_XLAT_SIZE) &&
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IS_ALIGNED(base_addr, (1UL << L1_ADDR_SHIFT))) {
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/* If block address is aligned and size is greater than
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* or equal to size addressed by each L1 entry, we can
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* directly store a block desc */
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desc = base_addr | BLOCK_DESC | attr;
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table[l1_index] = desc;
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/* L2 lookup is not required */
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return L1_XLAT_SIZE;
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} else {
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table = get_next_level_table(&table[l1_index]);
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if (!table)
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return 0;
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}
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}
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/*
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@ -213,10 +225,11 @@ static uint64_t init_xlat_table(uint64_t base_addr,
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* If lookup was performed at L1, L2 table addr is obtained from L1 desc
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* else, lookup starts at ttbr address
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*/
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if (!l3_index && (size >= L2_XLAT_SIZE)) {
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if ((size >= L2_XLAT_SIZE) &&
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IS_ALIGNED(base_addr, (1UL << L2_ADDR_SHIFT))) {
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/*
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* If block address is aligned and size is greater than or equal
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* to 512MiB i.e. size addressed by each L2 entry, we can
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* to size addressed by each L2 entry, we can
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* directly store a block desc
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*/
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desc = base_addr | BLOCK_DESC | attr;
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@ -369,7 +382,7 @@ void mmu_enable(void)
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/* Initialize TCR flags */
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raw_write_tcr_current(TCR_TOSZ | TCR_IRGN0_NM_WBWAC | TCR_ORGN0_NM_WBWAC |
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TCR_SH0_IS | TCR_TG0_64KB | TCR_PS_64GB |
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TCR_SH0_IS | TCR_TG0_4KB | TCR_PS_64GB |
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TCR_TBI_USED);
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/* Initialize TTBR */
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@ -49,14 +49,6 @@ struct mmu_ranges {
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*/
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extern char _start[], _end[];
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/* IMPORTANT!!!!!!!
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* Assumptions made:
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* Granule size is 64KiB
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* BITS per Virtual address is 33
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* All the calculations for tables L1,L2 and L3 are based on these assumptions
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* If these values are changed, recalculate the other macros as well
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*/
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/* Memory attributes for mmap regions
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* These attributes act as tag values for memrange regions
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*/
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@ -89,47 +81,32 @@ extern char _start[], _end[];
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/* XLAT Table Init Attributes */
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#define VA_START 0x0
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/* If BITS_PER_VA or GRANULE_SIZE are changed, recalculate and change the
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macros following them */
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#define BITS_PER_VA 33
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/* Granule size of 64KB is being used */
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#define MIN_64_BIT_ADDR (1UL << 32)
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#define XLAT_TABLE_MASK ~(0xffffUL)
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#define GRANULE_SIZE_SHIFT 16
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/* Granule size of 4KB is being used */
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#define GRANULE_SIZE_SHIFT 12
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#define GRANULE_SIZE (1 << GRANULE_SIZE_SHIFT)
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#define GRANULE_SIZE_MASK ((1 << 16) - 1)
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#define XLAT_TABLE_MASK (~(0UL) << GRANULE_SIZE_SHIFT)
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#define GRANULE_SIZE_MASK ((1 << GRANULE_SIZE_SHIFT) - 1)
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#define L1_ADDR_SHIFT 42
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#define L2_ADDR_SHIFT 29
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#define L3_ADDR_SHIFT 16
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#define BITS_RESOLVED_PER_LVL (GRANULE_SIZE_SHIFT - 3)
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#define L1_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL * 2)
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#define L2_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL * 1)
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#define L3_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL * 0)
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#define L1_ADDR_MASK (0UL << L1_ADDR_SHIFT)
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#define L2_ADDR_MASK (0xfUL << L2_ADDR_SHIFT)
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#define L3_ADDR_MASK (0x1fffUL << L3_ADDR_SHIFT)
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#if BITS_PER_VA > L1_ADDR_SHIFT + BITS_RESOLVED_PER_LVL
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#error "BITS_PER_VA too large (we don't have L0 table support)"
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#endif
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/* Dependent on BITS_PER_VA and GRANULE_SIZE */
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#define INIT_LEVEL 2
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#define XLAT_MAX_LEVEL 3
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/* Each entry in XLAT table is 8 bytes */
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#define XLAT_ENTRY_SHIFT 3
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#define XLAT_ENTRY_SIZE (1 << XLAT_ENTRY_SHIFT)
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#define XLAT_TABLE_SHIFT GRANULE_SIZE_SHIFT
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#define XLAT_TABLE_SIZE (1 << XLAT_TABLE_SHIFT)
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#define XLAT_NUM_ENTRIES_SHIFT (XLAT_TABLE_SHIFT - XLAT_ENTRY_SHIFT)
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#define XLAT_NUM_ENTRIES (1 << XLAT_NUM_ENTRIES_SHIFT)
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#define L3_XLAT_SIZE_SHIFT (GRANULE_SIZE_SHIFT)
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#define L2_XLAT_SIZE_SHIFT (GRANULE_SIZE_SHIFT + XLAT_NUM_ENTRIES_SHIFT)
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#define L1_XLAT_SIZE_SHIFT (GRANULE_SIZE_SHIFT + XLAT_NUM_ENTRIES_SHIFT)
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#define L1_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL) - 1) << L1_ADDR_SHIFT)
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#define L2_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL) - 1) << L2_ADDR_SHIFT)
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#define L3_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL) - 1) << L3_ADDR_SHIFT)
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/* These macros give the size of the region addressed by each entry of a xlat
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table at any given level */
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#define L3_XLAT_SIZE (1 << L3_XLAT_SIZE_SHIFT)
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#define L2_XLAT_SIZE (1 << L2_XLAT_SIZE_SHIFT)
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#define L1_XLAT_SIZE (1 << L1_XLAT_SIZE_SHIFT)
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#define L3_XLAT_SIZE (1UL << L3_ADDR_SHIFT)
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#define L2_XLAT_SIZE (1UL << L2_ADDR_SHIFT)
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#define L1_XLAT_SIZE (1UL << L1_ADDR_SHIFT)
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/* Block indices required for MAIR */
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#define BLOCK_INDEX_MEM_DEV_NGNRNE 0
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@ -184,7 +161,7 @@ extern char _start[], _end[];
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#define TCR_TBI_USED (0x0 << TCR_TBI_SHIFT)
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#define TCR_TBI_IGNORED (0x1 << TCR_TBI_SHIFT)
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#define DMA_DEFAULT_SIZE (0x200 * GRANULE_SIZE)
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#define DMA_DEFAULT_SIZE (32 * MiB)
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#define TTB_DEFAULT_SIZE 0x100000
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#define MB_SIZE (1UL << 20)
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@ -39,6 +39,7 @@
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#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
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#define ALIGN_UP(x,a) ALIGN((x),(a))
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#define ALIGN_DOWN(x,a) ((x) & ~((typeof(x))(a)-1UL))
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#define IS_ALIGNED(x,a) (((x) & ((typeof(x))(a)-1UL)) == 0)
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/**
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* @defgroup malloc Memory allocation functions
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