Add support for XHCI (USB 3.0)

CONFIG_HUDSON_XHCI_ENABLE will control the XHCI flags in the
amd/parmer and asus/f2a85-m mainboards.  The XHCI ports on
amd/thatcher are not wired to USB jacks so always disable the flags.
This was tested on amd/parmer using a USB 3.0 thumbdrive.

Change-Id: I596b040fec30882d8d4dee34ab9f866dc1f8896b
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/3465
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Dave Frodin 2013-06-13 17:30:48 -06:00 committed by Stefan Reinauer
parent 1fa1904e53
commit 0fd6a65243
5 changed files with 23 additions and 0 deletions

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@ -293,6 +293,14 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
/* Fan Control */ /* Fan Control */
oem_fan_control(FchParams_env); oem_fan_control(FchParams_env);
/* XHCI configuration */
#if CONFIG_HUDSON_XHCI_ENABLE
FchParams_env->Usb.Xhci0Enable = TRUE;
#else
FchParams_env->Usb.Xhci0Enable = FALSE;
#endif
FchParams_env->Usb.Xhci1Enable = FALSE;
/* sata configuration */ /* sata configuration */
} }
printk(BIOS_DEBUG, "Done\n"); printk(BIOS_DEBUG, "Done\n");

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@ -202,6 +202,10 @@ agesawrapper_amdinitreset (
AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct); AmdCreateStruct (&AmdParamStruct);
AmdResetParams.HtConfig.Depth = 0; AmdResetParams.HtConfig.Depth = 0;
#if !CONFIG_HUDSON_XHCI_ENABLE
AmdResetParams.FchInterface.Xhci0Enable = FALSE;
#endif
AmdResetParams.FchInterface.Xhci1Enable = FALSE;
status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);

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@ -202,6 +202,8 @@ agesawrapper_amdinitreset (
AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct); AmdCreateStruct (&AmdParamStruct);
AmdResetParams.HtConfig.Depth = 0; AmdResetParams.HtConfig.Depth = 0;
AmdResetParams.FchInterface.Xhci0Enable = FALSE;
AmdResetParams.FchInterface.Xhci1Enable = FALSE;
status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);

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@ -117,8 +117,13 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */ FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */
/* XHCI configuration */ /* XHCI configuration */
#if CONFIG_HUDSON_XHCI_ENABLE
FchParams_env->Usb.Xhci0Enable = TRUE; FchParams_env->Usb.Xhci0Enable = TRUE;
FchParams_env->Usb.Xhci1Enable = TRUE; FchParams_env->Usb.Xhci1Enable = TRUE;
#else
FchParams_env->Usb.Xhci0Enable = FALSE;
FchParams_env->Usb.Xhci1Enable = FALSE;
#endif
} }
printk(BIOS_DEBUG, "Done\n"); printk(BIOS_DEBUG, "Done\n");

View File

@ -202,6 +202,10 @@ agesawrapper_amdinitreset (
AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct); AmdCreateStruct (&AmdParamStruct);
AmdResetParams.HtConfig.Depth = 0; AmdResetParams.HtConfig.Depth = 0;
#if !CONFIG_HUDSON_XHCI_ENABLE
AmdResetParams.FchInterface.Xhci0Enable = FALSE;
AmdResetParams.FchInterface.Xhci1Enable = FALSE;
#endif
status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);