New Target and initial support for the Thomson IP1000.
Signed-off-by: Joseph Smith <joe@settoplinux.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Joseph Smith
Joseph Smith
parent
d9fa5d2aba
commit
0fd8ccd7e7
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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if USE_FALLBACK_IMAGE
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default ROM_SECTION_SIZE = FALLBACK_SIZE
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default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
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else
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default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
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default ROM_SECTION_OFFSET = 0
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end
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default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
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default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
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default XIP_ROM_SIZE = 65536
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default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
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arch i386 end
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driver mainboard.o
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if HAVE_PIRQ_TABLE object irq_tables.o end
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# object reset.o
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if HAVE_ACPI_TABLES
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object fadt.o
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object dsdt.o
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object acpi_tables.o
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end
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makerule ./failover.E
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depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
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action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
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end
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makerule ./failover.inc
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depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
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action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
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end
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makerule ./auto.E
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# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
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depends "$(MAINBOARD)/auto.c ./romcc"
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action "./romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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makerule ./auto.inc
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# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
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depends "$(MAINBOARD)/auto.c ./romcc"
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action "./romcc -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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mainboardinit cpu/x86/16bit/entry16.inc
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mainboardinit cpu/x86/32bit/entry32.inc
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ldscript /cpu/x86/16bit/entry16.lds
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ldscript /cpu/x86/32bit/entry32.lds
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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mainboardinit arch/i386/lib/cpu_reset.inc
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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mainboardinit ./failover.inc
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end
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mainboardinit cpu/x86/fpu/enable_fpu.inc
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mainboardinit cpu/x86/mmx/enable_mmx.inc
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mainboardinit ./auto.inc
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mainboardinit cpu/x86/mmx/disable_mmx.inc
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dir /pc80
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config chip.h
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chip northbridge/intel/i82830 # Northbridge
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device pci_domain 0 on # PCI domain
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device pci 0.0 on end # Host bridge
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chip drivers/pci/onboard # Onboard VGA
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device pci 2.0 on end # VGA (Intel 82830 CGC)
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register "rom_address" = "0xfff00000"
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end
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chip southbridge/intel/i82801xx # Southbridge
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device pci 1d.0 on end # USB UHCI Controller #1
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device pci 1d.1 on end # USB UHCI Controller #2
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device pci 1d.2 on end # USB UHCI Controller #3
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device pci 1d.7 on end # USB2 EHCI Controller
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device pci 1e.0 on # PCI bridge
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device pci 08.0 on end # Intel 82801DB PRO/100 VE Ethernet
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end
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device pci 1f.0 on # ISA/LPC bridge
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chip superio/smsc/smscsuperio # Super I/O
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device pnp 2e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.3 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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drq 0x74 = 4
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end
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device pnp 2e.4 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.5 on # Com2 / IR
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.7 on # PS/2 keyboard/mouse
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1 # Keyboard interrupt
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irq 0x72 = 12 # Mouse interrupt
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end
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device pnp 2e.9 off end # Game port
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device pnp 2e.a on # PME
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io 0x60 = 0x800
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end
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device pnp 2e.b off end # MPU-401
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end
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end
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device pci 1f.1 on end # IDE
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device pci 1f.3 on end # SMBus
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device pci 1f.5 on end # AC'97 audio
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device pci 1f.6 off end # AC'97 modem
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end
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end
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device apic_cluster 0 on # APIC cluster
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chip cpu/intel/socket_PGA370 # Low Voltage PIII Micro-FCBGA Socket 479
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device apic 0 on end # APIC
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end
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end
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end
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@ -0,0 +1,95 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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uses CC
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uses CONFIG_CONSOLE_SERIAL8250
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uses CONFIG_CONSOLE_VGA
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uses CONFIG_COMPRESSED_PAYLOAD_LZMA
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uses CONFIG_IOAPIC
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uses CONFIG_PCI_ROM_RUN
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uses CONFIG_ROM_PAYLOAD
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uses CONFIG_ROM_PAYLOAD_START
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uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
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uses CONFIG_UDELAY_TSC
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uses CONFIG_VIDEO_MB
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uses CROSS_COMPILE
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uses DEFAULT_CONSOLE_LOGLEVEL
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uses FALLBACK_SIZE
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uses HAVE_ACPI_TABLES
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uses HAVE_FALLBACK_BOOT
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uses HAVE_MP_TABLE
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uses HAVE_OPTION_TABLE
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uses HAVE_PIRQ_TABLE
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uses HEAP_SIZE
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uses HOSTCC
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uses IRQ_SLOT_COUNT
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uses COREBOOT_EXTRA_VERSION
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uses MAINBOARD
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uses MAINBOARD_VENDOR
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uses MAINBOARD_PART_NUMBER
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uses MAXIMUM_CONSOLE_LOGLEVEL
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uses OBJCOPY
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uses PAYLOAD_SIZE
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uses _RAMBASE
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uses _ROMBASE
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uses ROM_IMAGE_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_SECTION_OFFSET
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uses ROM_SIZE
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uses STACK_SIZE
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uses TTYS0_BASE
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uses TTYS0_BAUD
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uses TTYS0_LCS
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uses USE_FALLBACK_IMAGE
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uses USE_OPTION_TABLE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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default ROM_SIZE = 512 * 1024
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default ROM_IMAGE_SIZE = 128 * 1024
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default HAVE_FALLBACK_BOOT = 1
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default FALLBACK_SIZE = 256 * 1024
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default CONFIG_UDELAY_TSC = 1
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default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
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default HAVE_PIRQ_TABLE = 1
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default IRQ_SLOT_COUNT = 7
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default HAVE_MP_TABLE = 0
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default HAVE_ACPI_TABLES = 0
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default CONFIG_IOAPIC = 0
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default HAVE_OPTION_TABLE = 0
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default CONFIG_CONSOLE_VGA = 0
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default CONFIG_PCI_ROM_RUN = 0
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default CONFIG_VIDEO_MB = 0
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default STACK_SIZE = 0x2000
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default HEAP_SIZE = 0x4000
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default _RAMBASE = 0x00004000
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default USE_OPTION_TABLE = 0
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default CONFIG_ROM_PAYLOAD = 1
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default CC="$(CROSS_COMPILE)gcc -m32"
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default HOSTCC="gcc"
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default CONFIG_CONSOLE_SERIAL8250 = 1
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default TTYS0_BAUD = 115200
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default TTYS0_BASE = 0x3f8
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default TTYS0_LCS = 0x3 # 8n1
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default DEFAULT_CONSOLE_LOGLEVEL = 9
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default MAXIMUM_CONSOLE_LOGLEVEL = 9
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default MAINBOARD_VENDOR = "THOMSON"
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default MAINBOARD_PART_NUMBER = "IP1000"
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end
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@ -0,0 +1,126 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define ASSEMBLY 1
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#include <stdint.h>
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#include <stdlib.h>
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#include <device/pci_def.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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#include <arch/hlt.h>
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#include "pc80/serial.c"
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#include "pc80/udelay_io.c"
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
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#include "northbridge/intel/i82830/raminit.h"
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#include "northbridge/intel/i82830/memory_initialized.c"
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#include "southbridge/intel/i82801xx/i82801xx.h"
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#include "southbridge/intel/i82801xx/i82801xx_reset.c"
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#include "cpu/x86/mtrr/earlymtrr.c"
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#include "cpu/x86/bist.h"
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#include "spd_table.h"
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#include "gpio.c"
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#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
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#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c"
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#include "southbridge/intel/i82801xx/i82801xx_early_lpc.c"
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/**
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* The onboard 64MB PC133 memory does not have a SPD EEPROM so the
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* values have to be set manually, the SO-DIMM socket is located in
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* socket0 (0x50), and the onboard memory is located in socket1 (0x51).
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*/
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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int i;
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if (device == 0x50) {
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return smbus_read_byte(device, address);
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} else if (device == 0x51) {
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for (i = 0; i < ARRAY_SIZE(spd_table); i++) {
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if (spd_table[i].address == address)
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return spd_table[i].data;
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}
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return 0xFF; /* Return 0xFF when address is not found. */
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} else {
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return 0xFF; /* Return 0xFF on any failures. */
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}
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}
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#include "northbridge/intel/i82830/raminit.c"
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#include "sdram/generic_sdram.c"
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/**
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* The AC'97 Audio Controller I/O space registers are read only by default
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* so we need to enable them by setting register 0x41 to 0x01.
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*/
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static void ac97_io_enable(void)
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{
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device_t dev;
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/* Set the ac97 audio device staticly. */
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dev = PCI_DEV(0x0, 0x1f, 0x5);
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/* Enable access to the IO space. */
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pci_write_config8(dev, 0x41, 0x01);
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}
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static void main(unsigned long bist)
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{
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static const struct mem_controller memctrl[] = {
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{
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.d0 = PCI_DEV(0, 0, 0),
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.channel0 = {0x50, 0x51},
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}
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};
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if (bist == 0)
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early_mtrr_init();
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if (memory_initialized()) {
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hard_reset();
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}
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enable_smbus();
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smscsuperio_enable_serial(SERIAL_DEV, TTYS0_BASE);
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mb_gpio_init();
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uart_init();
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console_init();
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/* Prevent the TCO timer from rebooting us */
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i82801xx_halt_tco_timer();
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||||||
|
/* Halt if there was a built in self test failure. */
|
||||||
|
report_bist_failure(bist);
|
||||||
|
|
||||||
|
sdram_set_registers(memctrl);
|
||||||
|
sdram_set_spd_registers(memctrl);
|
||||||
|
sdram_enable(0, memctrl);
|
||||||
|
|
||||||
|
/* Check RAM. */
|
||||||
|
/* ram_check(0, 640 * 1024); */
|
||||||
|
/* ram_check(64512 * 1024, 65536 * 1024); */
|
||||||
|
|
||||||
|
ac97_io_enable();
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,25 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
extern struct chip_operations mainboard_thomson_ip1000_ops;
|
||||||
|
|
||||||
|
struct mainboard_thomson_ip1000_config {
|
||||||
|
int nothing;
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,120 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define PME_DEV PNP_DEV(0x2e, 0x0a)
|
||||||
|
#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */
|
||||||
|
#define ICH_IO_BASE_ADDR 0x00000500 /* GPIO base address register */
|
||||||
|
|
||||||
|
/* Early mainboard specific GPIO setup. */
|
||||||
|
static void mb_gpio_init(void)
|
||||||
|
{
|
||||||
|
device_t dev;
|
||||||
|
uint16_t port;
|
||||||
|
uint32_t set_gpio;
|
||||||
|
|
||||||
|
/* Southbridge GPIOs. */
|
||||||
|
/* Set the LPC device statically. */
|
||||||
|
dev = PCI_DEV(0x0, 0x1f, 0x0);
|
||||||
|
|
||||||
|
/* Set the value for GPIO base address register and enable GPIO. */
|
||||||
|
pci_write_config32(dev, GPIO_BASE_ICH0_5, (ICH_IO_BASE_ADDR | 1));
|
||||||
|
pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10);
|
||||||
|
|
||||||
|
/* Set GPIO25 to input and drive GPIO23 to high,
|
||||||
|
* this enables the LAN controller.
|
||||||
|
*/
|
||||||
|
udelay(10);
|
||||||
|
set_gpio = 0x0000ffff;
|
||||||
|
set_gpio |= 1 << 25;
|
||||||
|
outl(set_gpio, ICH_IO_BASE_ADDR + 0x04);
|
||||||
|
|
||||||
|
set_gpio = 0x1b3f0000;
|
||||||
|
set_gpio |= 1 << 23;
|
||||||
|
outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c);
|
||||||
|
|
||||||
|
/* Super I/O GPIOs. */
|
||||||
|
dev = PME_DEV;
|
||||||
|
port = dev >> 8;
|
||||||
|
|
||||||
|
outb(0x55, port); /* Enter the configuration state. */
|
||||||
|
pnp_set_logical_device(dev);
|
||||||
|
pnp_set_enable(dev, 0);
|
||||||
|
pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);
|
||||||
|
pnp_set_enable(dev, 1);
|
||||||
|
outl(0x03, PME_IO_BASE_ADDR + 0x1e); /* Force Disk Change */
|
||||||
|
outl(0x02, PME_IO_BASE_ADDR + 0x1f); /* Floppy Data Rate */
|
||||||
|
outl(0x81, PME_IO_BASE_ADDR + 0x20); /* UART1 FIFO */
|
||||||
|
outl(0x81, PME_IO_BASE_ADDR + 0x21); /* UART2 FIFO */
|
||||||
|
outl(0x00, PME_IO_BASE_ADDR + 0x22); /* Device Disable */
|
||||||
|
outl(0x01, PME_IO_BASE_ADDR + 0x23); /* GP10 */
|
||||||
|
outl(0x01, PME_IO_BASE_ADDR + 0x24); /* GP11 */
|
||||||
|
outl(0x01, PME_IO_BASE_ADDR + 0x25); /* GP12 */
|
||||||
|
outl(0x01, PME_IO_BASE_ADDR + 0x26); /* GP13 */
|
||||||
|
outl(0x01, PME_IO_BASE_ADDR + 0x27); /* GP14 */
|
||||||
|
outl(0x01, PME_IO_BASE_ADDR + 0x28); /* GP15 */
|
||||||
|
outl(0x01, PME_IO_BASE_ADDR + 0x29); /* GP16 */
|
||||||
|
outl(0x01, PME_IO_BASE_ADDR + 0x2a); /* GP17 */
|
||||||
|
outl(0x01, PME_IO_BASE_ADDR + 0x2b); /* GP20 */
|
||||||
|
outl(0x01, PME_IO_BASE_ADDR + 0x2c); /* GP21 */
|
||||||
|
outl(0x01, PME_IO_BASE_ADDR + 0x2d); /* GP22 */
|
||||||
|
outl(0x01, PME_IO_BASE_ADDR + 0x2f); /* GP24 */
|
||||||
|
outl(0x01, PME_IO_BASE_ADDR + 0x30); /* GP25 */
|
||||||
|
outl(0x01, PME_IO_BASE_ADDR + 0x31); /* GP26 */
|
||||||
|
outl(0x01, PME_IO_BASE_ADDR + 0x32); /* GP27 */
|
||||||
|
outl(0x05, PME_IO_BASE_ADDR + 0x33); /* GP30 */
|
||||||
|
outl(0x05, PME_IO_BASE_ADDR + 0x34); /* GP31 */
|
||||||
|
outl(0x84, PME_IO_BASE_ADDR + 0x35); /* GP32 */
|
||||||
|
outl(0x84, PME_IO_BASE_ADDR + 0x36); /* GP33 */
|
||||||
|
outl(0x00, PME_IO_BASE_ADDR + 0x37); /* GP34 */
|
||||||
|
outl(0x04, PME_IO_BASE_ADDR + 0x38); /* GP35 */
|
||||||
|
outl(0x01, PME_IO_BASE_ADDR + 0x39); /* GP36 */
|
||||||
|
outl(0x01, PME_IO_BASE_ADDR + 0x3a); /* GP37 */
|
||||||
|
outl(0x01, PME_IO_BASE_ADDR + 0x3b); /* GP40 */
|
||||||
|
outl(0x01, PME_IO_BASE_ADDR + 0x3c); /* GP41 */
|
||||||
|
outl(0x86, PME_IO_BASE_ADDR + 0x3d); /* GP42 */
|
||||||
|
outl(0x01, PME_IO_BASE_ADDR + 0x3e); /* GP43 */
|
||||||
|
outl(0x05, PME_IO_BASE_ADDR + 0x3f); /* GP50 */
|
||||||
|
outl(0x05, PME_IO_BASE_ADDR + 0x40); /* GP51 */
|
||||||
|
outl(0x05, PME_IO_BASE_ADDR + 0x41); /* GP52 */
|
||||||
|
outl(0x04, PME_IO_BASE_ADDR + 0x42); /* GP53 */
|
||||||
|
outl(0x05, PME_IO_BASE_ADDR + 0x43); /* GP54 */
|
||||||
|
outl(0x04, PME_IO_BASE_ADDR + 0x44); /* GP55 */
|
||||||
|
outl(0x05, PME_IO_BASE_ADDR + 0x45); /* GP56 */
|
||||||
|
outl(0x04, PME_IO_BASE_ADDR + 0x46); /* GP57 */
|
||||||
|
outl(0x01, PME_IO_BASE_ADDR + 0x47); /* GP58 */
|
||||||
|
outl(0x01, PME_IO_BASE_ADDR + 0x48); /* GP59 */
|
||||||
|
outl(0x00, PME_IO_BASE_ADDR + 0x4b); /* GP1 */
|
||||||
|
outl(0x04, PME_IO_BASE_ADDR + 0x4c); /* GP2 */
|
||||||
|
outl(0xc0, PME_IO_BASE_ADDR + 0x4d); /* GP3 */
|
||||||
|
outl(0x00, PME_IO_BASE_ADDR + 0x4e); /* GP4 */
|
||||||
|
outl(0x04, PME_IO_BASE_ADDR + 0x4f); /* GP5 */
|
||||||
|
outl(0x00, PME_IO_BASE_ADDR + 0x50); /* GP6 */
|
||||||
|
outl(0x01, PME_IO_BASE_ADDR + 0x56); /* FAN1 */
|
||||||
|
outl(0x01, PME_IO_BASE_ADDR + 0x57); /* FAN2 */
|
||||||
|
outl(0x58, PME_IO_BASE_ADDR + 0x58); /* Fan Control */
|
||||||
|
outl(0xff, PME_IO_BASE_ADDR + 0x59); /* Fan1 Tachometer */
|
||||||
|
outl(0x50, PME_IO_BASE_ADDR + 0x5a); /* Fan2 Tachometer */
|
||||||
|
outl(0x00, PME_IO_BASE_ADDR + 0x5b); /* Fan1 Preload */
|
||||||
|
outl(0x00, PME_IO_BASE_ADDR + 0x5c); /* Fan2 Preload */
|
||||||
|
outl(0x00, PME_IO_BASE_ADDR + 0x5d); /* LED1 */
|
||||||
|
outl(0x00, PME_IO_BASE_ADDR + 0x5e); /* LED2 */
|
||||||
|
outl(0x00, PME_IO_BASE_ADDR + 0x5f); /* Keyboard Scan Code */
|
||||||
|
outb(0xaa, port); /* Exit the configuration state. */
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <arch/pirq_routing.h>
|
||||||
|
|
||||||
|
const struct irq_routing_table intel_irq_routing_table = {
|
||||||
|
PIRQ_SIGNATURE, /* u32 signature */
|
||||||
|
PIRQ_VERSION, /* u16 version */
|
||||||
|
32+16*IRQ_SLOT_COUNT, /* there can be total 7 devices on the bus */
|
||||||
|
0x00, /* Where the interrupt router lies (bus) */
|
||||||
|
(0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */
|
||||||
|
0, /* IRQs devoted exclusively to PCI usage */
|
||||||
|
0x8086, /* Vendor */
|
||||||
|
0x24c0, /* Device */
|
||||||
|
0, /* Crap (miniport) */
|
||||||
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||||
|
0xcd, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||||
|
{
|
||||||
|
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||||
|
{0x00,(0x02<<3)|0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] VGA compatible controller */
|
||||||
|
{0x00,(0x1d<<3)|0x0, {{0x60, 0x1ef8}, {0x63, 0x1ef8}, {0x62, 0x1ef8}, {0x6b, 0x01ef8}}, 0x0, 0x0}, /* [D] USB2 EHCI Controller */
|
||||||
|
{0x00,(0x1f<<3)|0x0, {{0x62, 0x1ef8}, {0x61, 0x1ef8}, {0x6b, 0x1ef8}, {0x63, 0x01ef8}}, 0x0, 0x0}, /* [A] IDE Controller */
|
||||||
|
{0x01,(0x08<<3)|0x0, {{0x68, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] Ethernet controller */
|
||||||
|
{0x01,(0x00<<3)|0x0, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x01ef8}}, 0x1, 0x0}, /* [A] USB UHCI Controller #1 */
|
||||||
|
{0x01,(0x01<<3)|0x0, {{0x63, 0x1ef8}, {0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x01ef8}}, 0x2, 0x0}, /* [B] USB UHCI Controller #2 */
|
||||||
|
{0x01,(0x02<<3)|0x0, {{0x62, 0x1ef8}, {0x63, 0x1ef8}, {0x60, 0x1ef8}, {0x61, 0x01ef8}}, 0x3, 0x0}, /* [C] USB UHCI Controller #3 */
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||||
|
{
|
||||||
|
return copy_pirq_routing_table(addr);
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,26 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <device/device.h>
|
||||||
|
#include "chip.h"
|
||||||
|
|
||||||
|
struct chip_operations mainboard_thomson_ip1000_ops = {
|
||||||
|
CHIP_NAME("THOMSON IP1000 Mainboard")
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,40 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <spd.h>
|
||||||
|
|
||||||
|
struct spd_entry {
|
||||||
|
unsigned int address;
|
||||||
|
unsigned int data;
|
||||||
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The onboard 64MB PC133 memory does not have an SPD EEPROM so the values
|
||||||
|
* have to be set manually, the onboard memory is located in socket1 (0x51).
|
||||||
|
*/
|
||||||
|
const struct spd_entry spd_table [] = {
|
||||||
|
{SPD_MEMORY_TYPE, 0x04}, /* (Fundamental) memory type */
|
||||||
|
{SPD_NUM_COLUMNS, 0x09}, /* Number of column address bits */
|
||||||
|
{SPD_NUM_DIMM_BANKS, 0x01}, /* Number of module rows (banks) */
|
||||||
|
{SPD_MODULE_DATA_WIDTH_LSB, 0x40}, /* Module data width (LSB) */
|
||||||
|
{SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 0x75}, /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */
|
||||||
|
{SPD_ACCESS_TIME_FROM_CLOCK, 0x54}, /* SDRAM access time from clock (highest CAS latency), CAS access time (Tac, tCAC) */
|
||||||
|
{SPD_DENSITY_OF_EACH_ROW_ON_MODULE, 0x10}, /* Density of each row on module */
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,30 @@
|
||||||
|
##
|
||||||
|
## This file is part of the coreboot project.
|
||||||
|
##
|
||||||
|
## Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
|
||||||
|
##
|
||||||
|
## This program is free software; you can redistribute it and/or modify
|
||||||
|
## it under the terms of the GNU General Public License as published by
|
||||||
|
## the Free Software Foundation; either version 2 of the License, or
|
||||||
|
## (at your option) any later version.
|
||||||
|
##
|
||||||
|
## This program is distributed in the hope that it will be useful,
|
||||||
|
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
## GNU General Public License for more details.
|
||||||
|
##
|
||||||
|
## You should have received a copy of the GNU General Public License
|
||||||
|
## along with this program; if not, write to the Free Software
|
||||||
|
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
##
|
||||||
|
|
||||||
|
target thomson_ip1000
|
||||||
|
mainboard thomson/ip1000
|
||||||
|
|
||||||
|
romimage "fallback"
|
||||||
|
option USE_FALLBACK_IMAGE = 1
|
||||||
|
payload __PAYLOAD__
|
||||||
|
end
|
||||||
|
|
||||||
|
buildrom ./coreboot.rom ROM_SIZE "fallback"
|
||||||
|
|
||||||
|
|
@ -0,0 +1,63 @@
|
||||||
|
##
|
||||||
|
## This file is part of the coreboot project.
|
||||||
|
##
|
||||||
|
## Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
|
||||||
|
##
|
||||||
|
## This program is free software; you can redistribute it and/or modify
|
||||||
|
## it under the terms of the GNU General Public License as published by
|
||||||
|
## the Free Software Foundation; either version 2 of the License, or
|
||||||
|
## (at your option) any later version.
|
||||||
|
##
|
||||||
|
## This program is distributed in the hope that it will be useful,
|
||||||
|
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
## GNU General Public License for more details.
|
||||||
|
##
|
||||||
|
## You should have received a copy of the GNU General Public License
|
||||||
|
## along with this program; if not, write to the Free Software
|
||||||
|
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
##
|
||||||
|
|
||||||
|
target ip1000
|
||||||
|
mainboard thomson/ip1000
|
||||||
|
|
||||||
|
##
|
||||||
|
## Total number of bytes allocated for coreboot use
|
||||||
|
## (fallback images and payloads).
|
||||||
|
##
|
||||||
|
# option ROM_SIZE = 1024 * 1024
|
||||||
|
## For VGA BIOS (-64k)
|
||||||
|
option ROM_SIZE = (1024 * 1024) - (64 * 1024)
|
||||||
|
|
||||||
|
##
|
||||||
|
## VGA Console
|
||||||
|
## NOTE: to initialize VGA, you need to copy
|
||||||
|
## the VGA option ROM from the factory BIOS
|
||||||
|
## 0=disable 1=enable
|
||||||
|
##
|
||||||
|
option CONFIG_CONSOLE_VGA = 1
|
||||||
|
option CONFIG_PCI_ROM_RUN = 1
|
||||||
|
|
||||||
|
##
|
||||||
|
## Choose the amount of memory pre-allocated for VGA
|
||||||
|
## 0 for No memory pre-allocated (Graphics memory Disabled)
|
||||||
|
## 512 for DVMT (UMA) mode, 512K of memory pre-allocated for frame buffer
|
||||||
|
## 1 for DVMT (UMA) mode, 1M of memory pre-allocated for frame buffer
|
||||||
|
## 8 for DVMT (UMA) mode, 8M of memory pre-allocated for frame buffer
|
||||||
|
##
|
||||||
|
option CONFIG_VIDEO_MB = 8
|
||||||
|
|
||||||
|
##
|
||||||
|
## Request this level of debugging output
|
||||||
|
##
|
||||||
|
option DEFAULT_CONSOLE_LOGLEVEL = 7
|
||||||
|
|
||||||
|
romimage "fallback"
|
||||||
|
option USE_FALLBACK_IMAGE = 1
|
||||||
|
option FALLBACK_SIZE = ROM_SIZE
|
||||||
|
option COREBOOT_EXTRA_VERSION = "_IP1000"
|
||||||
|
payload /tmp/filo.elf
|
||||||
|
# payload /tmp/eb-5.4.3-eepro100.elf
|
||||||
|
end
|
||||||
|
|
||||||
|
buildrom ./coreboot.rom ROM_SIZE "fallback"
|
||||||
Loading…
Reference in New Issue