soc/amd/picasso: add devicetree setting for PSPP policy

Since the default for the corresponding UPD of the Picasso FSP is
DXIO_PSPP_POWERSAVE and the devicetree default is DXIO_PSPP_PERFORMANCE,
add a deviectree setting for each board that's using the Picasso SoC
code to not change the setting for the existing boards.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0008ebb0c0f339ed3bdf24ab95a20aa83d5be2c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Felix Held 2021-05-25 21:07:23 +02:00
parent 6a936fc6ae
commit 0fec867e32
7 changed files with 20 additions and 0 deletions

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@ -136,6 +136,8 @@ chip soc/amd/picasso
register "gpp_clk_config[5]" = "GPP_CLK_REQ"
register "gpp_clk_config[6]" = "GPP_CLK_REQ"
register "pspp_policy" = "DXIO_PSPP_POWERSAVE"
device cpu_cluster 0 on
device lapic 0 on end
end

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@ -136,6 +136,8 @@ chip soc/amd/picasso
register "gpp_clk_config[5]" = "GPP_CLK_OFF"
register "gpp_clk_config[6]" = "GPP_CLK_OFF"
register "pspp_policy" = "DXIO_PSPP_POWERSAVE"
device cpu_cluster 0 on
device lapic 0 on end
end

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@ -136,6 +136,8 @@ chip soc/amd/picasso
register "gpp_clk_config[5]" = "GPP_CLK_REQ"
register "gpp_clk_config[6]" = "GPP_CLK_REQ"
register "pspp_policy" = "DXIO_PSPP_POWERSAVE"
device cpu_cluster 0 on
device lapic 0 on end
end

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@ -250,6 +250,8 @@ chip soc/amd/picasso
register "gpp_clk_config[5]" = "GPP_CLK_OFF"
register "gpp_clk_config[6]" = "GPP_CLK_OFF"
register "pspp_policy" = "DXIO_PSPP_POWERSAVE"
device cpu_cluster 0 on
device lapic 0 on end
end

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@ -243,6 +243,8 @@ chip soc/amd/picasso
register "gpp_clk_config[5]" = "GPP_CLK_OFF"
register "gpp_clk_config[6]" = "GPP_CLK_OFF"
register "pspp_policy" = "DXIO_PSPP_POWERSAVE"
device cpu_cluster 0 on
device lapic 0 on end
end

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@ -263,6 +263,13 @@ struct soc_amd_picasso_config {
GPP_CLK_OFF, /* GPP clk off */
} gpp_clk_config[GPP_CLK_OUTPUT_COUNT];
/* performance policy for the PCIe links: power consumption vs. link speed */
enum {
DXIO_PSPP_PERFORMANCE = 0,
DXIO_PSPP_BALANCED,
DXIO_PSPP_POWERSAVE,
} pspp_policy;
/* If using an external 48MHz OSC for codec, will disable internal X48M_OSC */
bool acp_i2s_use_external_48mhz_osc;

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@ -112,5 +112,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
mcfg->sata_enable = devtree_sata_dev_enabled();
mcfg->hdmi2_disable = config->hdmi2_disable;
/* PCIe power vs. speed */
mcfg->pspp_policy = config->pspp_policy;
mainboard_updm_update(mcfg);
}