soc/amd/picasso: add devicetree setting for PSPP policy
Since the default for the corresponding UPD of the Picasso FSP is DXIO_PSPP_POWERSAVE and the devicetree default is DXIO_PSPP_PERFORMANCE, add a deviectree setting for each board that's using the Picasso SoC code to not change the setting for the existing boards. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0008ebb0c0f339ed3bdf24ab95a20aa83d5be2c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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@ -136,6 +136,8 @@ chip soc/amd/picasso
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register "gpp_clk_config[5]" = "GPP_CLK_REQ"
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register "gpp_clk_config[6]" = "GPP_CLK_REQ"
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register "pspp_policy" = "DXIO_PSPP_POWERSAVE"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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@ -136,6 +136,8 @@ chip soc/amd/picasso
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register "gpp_clk_config[5]" = "GPP_CLK_OFF"
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register "gpp_clk_config[6]" = "GPP_CLK_OFF"
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register "pspp_policy" = "DXIO_PSPP_POWERSAVE"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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@ -136,6 +136,8 @@ chip soc/amd/picasso
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register "gpp_clk_config[5]" = "GPP_CLK_REQ"
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register "gpp_clk_config[6]" = "GPP_CLK_REQ"
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register "pspp_policy" = "DXIO_PSPP_POWERSAVE"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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@ -250,6 +250,8 @@ chip soc/amd/picasso
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register "gpp_clk_config[5]" = "GPP_CLK_OFF"
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register "gpp_clk_config[6]" = "GPP_CLK_OFF"
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register "pspp_policy" = "DXIO_PSPP_POWERSAVE"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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@ -243,6 +243,8 @@ chip soc/amd/picasso
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register "gpp_clk_config[5]" = "GPP_CLK_OFF"
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register "gpp_clk_config[6]" = "GPP_CLK_OFF"
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register "pspp_policy" = "DXIO_PSPP_POWERSAVE"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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@ -263,6 +263,13 @@ struct soc_amd_picasso_config {
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GPP_CLK_OFF, /* GPP clk off */
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} gpp_clk_config[GPP_CLK_OUTPUT_COUNT];
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/* performance policy for the PCIe links: power consumption vs. link speed */
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enum {
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DXIO_PSPP_PERFORMANCE = 0,
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DXIO_PSPP_BALANCED,
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DXIO_PSPP_POWERSAVE,
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} pspp_policy;
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/* If using an external 48MHz OSC for codec, will disable internal X48M_OSC */
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bool acp_i2s_use_external_48mhz_osc;
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@ -112,5 +112,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
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mcfg->sata_enable = devtree_sata_dev_enabled();
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mcfg->hdmi2_disable = config->hdmi2_disable;
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/* PCIe power vs. speed */
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mcfg->pspp_policy = config->pspp_policy;
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mainboard_updm_update(mcfg);
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}
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