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exynos5420: Set the CLK_DIV_CPERI1 value as per manual 

Set the CLK_DIV_CPERI1 value as recommended by the
0.02 UM section 7.9.1.25.
This suggests to use 0x3F3F0000 as the value to be
set to save power.

This is ported from https://gerrit.chromium.org/gerrit/#/c/64905
Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I89a6a72d20374a513019a272628a05e139b31773
Reviewed-on: https://gerrit.chromium.org/gerrit/66787
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
(cherry picked from commit 34be13b008e262c641268b7c1c6a08e49f18fc37)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6512
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
David Hendricks 2013-08-22 16:52:38 -07:00 committed by Isaac Christensen
parent ee4bfbf3e1
commit 0ffa11bdbb
2 changed files with 4 additions and 0 deletions
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2
src/cpu/samsung/exynos5420/clock_init.c
View File

@ -209,6 +209,8 @@ void system_clock_init(void)
writel(CLK_DIV_PERIC3_VAL, &clk->clk_div_peric3);
writel(CLK_DIV_PERIC4_VAL, &clk->clk_div_peric4);
writel(CLK_DIV_CPERI1_VAL, &clk->clk_div_cperi1);
writel(CLK_DIV2_RATIO, &clk->clkdiv2_ratio);
writel(CLK_DIV4_RATIO, &clk->clkdiv4_ratio);
writel(CLK_DIV_G2D, &clk->clk_div_g2d);

2
src/cpu/samsung/exynos5420/setup.h
View File

@ -48,6 +48,8 @@ struct exynos5_phy_control;
#define APLL_FOUT (1 << 0)
#define KPLL_FOUT (1 << 0)
#define CLK_DIV_CPERI1_VAL 0x3f3f0000
/* APLL_CON1 */
#define APLL_CON1_VAL (0x0020f300)