First bunch of coding style and consistency cleanups for the
EPIA-M700 target. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4349 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
parent
cff071ab0e
commit
0ffff3434e
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@ -28,19 +28,19 @@ driver wakeup.o
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if HAVE_PIRQ_TABLE object irq_tables.o end
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_ACPI_TABLES
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object fadt.o
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object dsdt.o
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# object ssdt.o
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object acpi_tables.o
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object fadt.o
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object dsdt.o
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# object ssdt.o
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object acpi_tables.o
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end
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# these lines maybe noused
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# These lines maybe noused.
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makerule ./failover.E
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depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
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action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
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depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
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action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
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end
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makerule ./failover.inc
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depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
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action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
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depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
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action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
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end
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if USE_DCACHE_RAM
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if CONFIG_USE_INIT
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@ -60,22 +60,23 @@ end
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mainboardinit cpu/via/16bit/entry16.inc
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ldscript /cpu/via/16bit/entry16.lds
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mainboardinit northbridge/via/vx800/romstrap.inc
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mainboardinit northbridge/via/vx800/romstrap.inc
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ldscript /northbridge/via/vx800/romstrap.lds
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mainboardinit cpu/x86/32bit/entry32.inc
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ldscript /cpu/x86/32bit/entry32.lds
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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#mainboardinit arch/i386/lib/cpu_reset.inc
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#here cpu_reset.inc have label _cpu_reset, which is needed in failover,c, but cpu_reset.inc also has code to jump to __main() which is not included in cache_as_ram_auto_auto.c
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# mainboardinit arch/i386/lib/cpu_reset.inc
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# Here cpu_reset.inc have label _cpu_reset, which is needed in failover.c,
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# but cpu_reset.inc also has code to jump to __main() which is not included
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# in cache_as_ram_auto_auto.c.
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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@ -85,13 +86,13 @@ if USE_DCACHE_RAM
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end
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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# failover.inc need defination in cpu_reset.inc, but we do not include cpu_reset.inc,so ...
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# mainboardinit ./failover.inc
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ldscript /arch/i386/lib/failover.lds
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# failover.inc need definition in cpu_reset.inc, but we do not include
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# cpu_reset.inc,so ...
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# mainboardinit ./failover.inc
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end
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#mainboardinit cpu/x86/fpu/enable_fpu.inc
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#mainboardinit cpu/x86/mmx/enable_mmx.inc
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# mainboardinit cpu/x86/fpu/enable_fpu.inc
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# mainboardinit cpu/x86/mmx/enable_mmx.inc
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if USE_DCACHE_RAM
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if CONFIG_USE_INIT
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@ -100,35 +101,33 @@ if USE_DCACHE_RAM
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mainboardinit ./cache_as_ram_auto.inc
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end
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end
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#mainboardinit cpu/x86/mmx/disable_mmx.inc
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# mainboardinit cpu/x86/mmx/disable_mmx.inc
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dir /pc80
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config chip.h
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chip northbridge/via/vx800 # Northbridge
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device pci_domain 0 on
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device pci 0.0 on end # AGP Bridge
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device pci 0.1 on end # Error Reporting
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device pci 0.2 on end # Host Bus Control
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device pci 0.3 on end # Memory Controller
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device pci 0.4 on end # Power Management
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device pci 0.7 on end # V-Link Controller
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device pci 1.0 on end # PCI Bridge
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#device pci f.0 on end # IDE/SATA
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#device pci f.1 on end # IDE
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#device pci 10.0 on end # USB 1.1
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#device pci 10.1 on end # USB 1.1
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#device pci 10.2 on end # USB 1.1
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#device pci 10.4 on end # USB 2.0
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#device pci 11.0 on # Southbridge LPC
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#end # pci 11.0
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end # pci domain 0
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device apic_cluster 0 on # APIC cluster
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chip cpu/via/model_c7 # VIA C7
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device apic 0 on end # APIC
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end
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end
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end # vx800
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device pci_domain 0 on
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device pci 0.0 on end # AGP Bridge
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device pci 0.1 on end # Error Reporting
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device pci 0.2 on end # Host Bus Control
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device pci 0.3 on end # Memory Controller
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device pci 0.4 on end # Power Management
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device pci 0.7 on end # V-Link Controller
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device pci 1.0 on end # PCI Bridge
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# device pci f.0 on end # IDE/SATA
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# device pci f.1 on end # IDE
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# device pci 10.0 on end # USB 1.1
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# device pci 10.1 on end # USB 1.1
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# device pci 10.2 on end # USB 1.1
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# device pci 10.4 on end # USB 2.0
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# device pci 11.0 on # Southbridge LPC
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# end
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end
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device apic_cluster 0 on # APIC cluster
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chip cpu/via/model_c7 # VIA C7
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device apic 0 on end # APIC
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end
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end
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end
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@ -17,230 +17,221 @@
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "northbridge/via/vx800/DrivingClkPhaseData.h"
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// DQS Driving
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//Reg0xE0, 0xE1
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// DQS Driving
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// Reg0xE0, 0xE1
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// According to #Bank to set DRAM DQS Driving
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// #Bank 1 2 3 4 5 6 7 8
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static const u8 DDR2_DQSA_Driving_Table[4] = { 0xEE, 0xEE, 0xEE, 0xEE};
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static const u8 DDR2_DQSB_Driving_Table[2] = { 0xEE, 0xEE};
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// #Bank 1 2 3 4 5 6 7 8
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static const u8 DDR2_DQSA_Driving_Table[4] = { 0xEE, 0xEE, 0xEE, 0xEE };
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static const u8 DDR2_DQSB_Driving_Table[2] = { 0xEE, 0xEE };
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// DQ Driving
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//Reg0xE2, 0xE3
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// For DDR2: According to bank to set DRAM DQ Driving
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static const u8 DDR2_DQA_Driving_Table[4] = { 0xAC, 0xAC, 0xAC, 0xAC };
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static const u8 DDR2_DQB_Driving_Table[2] = { 0xCA, 0xCA };
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// Reg0xE2, 0xE3
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// For DDR2: According to bank to set DRAM DQ Driving
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static const u8 DDR2_DQA_Driving_Table[4] = { 0xAC, 0xAC, 0xAC, 0xAC };
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static const u8 DDR2_DQB_Driving_Table[2] = { 0xCA, 0xCA };
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// CS Driving
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//Reg0xE4, 0xE5
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// CS Driving
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// Reg0xE4, 0xE5
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// According to #Bank to set DRAM CS Driving
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// DDR1 #Bank 1 2 3 4 5 6 7 8
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static const u8 DDR2_CSA_Driving_Table_x8[4] = { 0x44, 0x44, 0x44, 0x44 };
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static const u8 DDR2_CSB_Driving_Table_x8[2] = { 0x44, 0x44};
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static const u8 DDR2_CSA_Driving_Table_x16[4]= { 0x44, 0x44, 0x44, 0x44};
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static const u8 DDR2_CSB_Driving_Table_x16[2]= { 0x44, 0x44};
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// MAA Driving
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//Reg0xE8, Reg0xE9
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static const u8 DDR2_MAA_Driving_Table[MA_Table][5] =
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{
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//Chip number, 400, 533, 667 800 ;(SRAS, SCAS, SWE)RxE8
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{ 6, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 00 ~ 06
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{ 18, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 06 ~ 18
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{255, 0xDB, 0xDB, 0xDB, 0xDB} // total MAA chips = 18 ~
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};
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// DDR1 #Bank 1 2 3 4 5 6 7 8
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static const u8 DDR2_CSA_Driving_Table_x8[4] = { 0x44, 0x44, 0x44, 0x44 };
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static const u8 DDR2_CSB_Driving_Table_x8[2] = { 0x44, 0x44 };
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static const u8 DDR2_CSA_Driving_Table_x16[4] = { 0x44, 0x44, 0x44, 0x44 };
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static const u8 DDR2_CSB_Driving_Table_x16[2] = { 0x44, 0x44 };
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static const u8 DDR2_MAB_Driving_Table[MA_Table][2] =
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{
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// Chip number, Value ;(SRAS, SCAS, SWE)RxE9
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{ 6, 0x86 }, // total MAB chips = 00 ~ 06
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{ 18, 0x86 }, // total MAB chips = 06 ~ 18
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{255, 0xDB } // total MAB chips = 18 ~
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};
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// MAA Driving
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// Reg0xE8, Reg0xE9
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static const u8 DDR2_MAA_Driving_Table[MA_Table][5] = {
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// Chip number, 400, 533, 667 800 ;(SRAS, SCAS, SWE)RxE8
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{6, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 00 ~ 06
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{18, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 06 ~ 18
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{255, 0xDB, 0xDB, 0xDB, 0xDB}, // total MAA chips = 18 ~
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};
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static const u8 DDR2_MAB_Driving_Table[MA_Table][2] = {
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// Chip number, Value ;(SRAS, SCAS, SWE)RxE9
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{6, 0x86}, // total MAB chips = 00 ~ 06
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{18, 0x86}, // total MAB chips = 06 ~ 18
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{255, 0xDB}, // total MAB chips = 18 ~
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};
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// DCLK Driving
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//Reg0xE6, 0xE7
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// Reg0xE6, 0xE7
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// For DDR2: According to #Freq to set DRAM DCLK Driving
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// freq 400M, 533M, 667M, 800M
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static const u8 DDR2_DCLKA_Driving_Table[4] = { 0xFF, 0xFF, 0xFF, 0xFF };
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static const u8 DDR2_DCLKB_Driving_Table[4] = { 0xFF, 0xFF, 0xFF, 0xFF };
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// freq 400M, 533M, 667M, 800M
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static const u8 DDR2_DCLKA_Driving_Table[4] = { 0xFF, 0xFF, 0xFF, 0xFF };
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static const u8 DDR2_DCLKB_Driving_Table[4] = { 0xFF, 0xFF, 0xFF, 0xFF };
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/*
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Duty cycle
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Duty cycle Control for DQ/DQS/DDRCKG in ChA & ChB
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D0F3RxEC/D0F3RxED/D0F3RxEE/D0F3RxEF
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According to DRAM frequency to control Duty Cycle
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*/
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static const u8 ChA_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM] =
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{
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// (And NOT) DDR800 DDR667 DDR533 DDR400
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//Reg Mask Value Value Value Value
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{0xEC, 0x00, 0x30, 0x30, 0x30, 0x30 }, // 1Rank
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{0xEE, 0x0F, 0x40, 0x40, 0x00, 0x00 },
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{0xEF, 0xCF, 0x00, 0x30, 0x30, 0x30}
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};
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static const u8 ChB_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM] =
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{
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// (And NOT) DDR800 DDR667 DDR533 DDR400
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//Reg Mask Value Value Value Value
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{0xED, 0x00, 0x88, 0x88, 0x84, 0x88 }, // 1Rank
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{0xEE, 0xF0, 0x00, 0x00, 0x00, 0x00 },
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{0xEF, 0xFC, 0x00, 0x00, 0x00, 0x00 }
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};
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/*
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DRAM Clock Phase Control for FeedBack Mode
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Modify NB Reg: Rx90[7]/Rx91/Rx92/Rx93/Rx94
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Processing:
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1.Program VIA_NB3DRAM_REG90[7]=0b for FeedBack mode
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2.Program clock phase value with ChA/B DCLK enable, VIA_NB3DRAM_REG91[7:3]=00b
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3.Check ChB rank #, if 0, VIA_NB3DRAM_REG91[7]=1b, to disable ChB DCLKO
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ChA DCLKO can not be disable, so always program VIA_NB3DRAM_REG91[3]=0b
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* Duty cycle
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* Duty cycle Control for DQ/DQS/DDRCKG in ChA & ChB
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* D0F3RxEC/D0F3RxED/D0F3RxEE/D0F3RxEF
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* According to DRAM frequency to control Duty Cycle
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*/
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static const u8 DDR2_ChA_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width] =
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{
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// (And NOT) DDR800 DDR667 DDR533 DDR400
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//Reg Mask Value Value Value Value
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{0x91, 0xF8, 0x02, 0x01, 0x00, 0x07 }, // 1Rank
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{0x92, 0xF8, 0x04, 0x03, 0x03, 0x02 },
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{0x93, 0xF8, 0x06, 0x05, 0x04, 0x03 }
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};
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static const u8 DDR2_ChB_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width] =
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{
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// (And NOT) DDR800 DDR667 DDR533 DDR400
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//Reg Mask Value Value Value Value
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{0x91, 0x0F, 0x20, 0x10, 0x00, 0x70 }, // 1Rank
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{0x92, 0x0F, 0x40, 0x30, 0x30, 0x20 },
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{0x93, 0x0F, 0x60, 0x50, 0x40, 0x30 }
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};
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//vt6413c
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/*static const u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width] =
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{
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// (And NOT) DDR800 DDR667 DDR533 DDR400
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//Reg Mask Value Value Value Value
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{0x91, 0xF8, 0x04, 0x03, 0x04, 0x01 }, // 1Rank
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{0x92, 0xF8, 0x03, 0x06, 0x05, 0x04 },
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{0x93, 0xF8, 0x03, 0x07, 0x06, 0x05 }
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};*/
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//vt6413d
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static const u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width] =
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{
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// (And NOT) DDR800 DDR667 DDR533 DDR400
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//Reg Mask Value Value Value Value
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{0x91, 0xF8, 0x02, 0x01, 0x00, 0x07}, // 1Rank
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{0x92, 0xF8, 0x04, 0x03, 0x03, 0x02 },
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{0x93, 0xF8, 0x06, 0x05, 0x04, 0x03 }
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};
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/*
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DRAM Write Data phase control
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Modify NB Reg: Rx74/Rx75/Rx76
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*/
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//vt6413c
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/*static const u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] =
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{
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// (And NOT) DDR800 DDR667 DDR533 DDR400
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//Reg Mask Value Value Value Value
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{0x74, 0xF8, 0x03, 0x04, 0x05, 0x02 }, // 1Rank
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{0x75, 0xF8, 0x03, 0x04, 0x05, 0x02 },
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{0x76, 0x00, 0x10, 0x80, 0x00, 0x07 }
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};*/
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//vt6413D
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static const u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] =
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{
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// (And NOT) DDR800 DDR667 DDR533 DDR400
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//Reg Mask Value Value Value Value
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{0x74, 0xF8, 0x01, 0x00, 0x00, 0x07 }, // 1Rank
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{0x75, 0xF8, 0x01, 0x00, 0x00, 0x07 },
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{0x76, 0x10, 0x80, 0x87, 0x07, 0x06 },
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{0x8C, 0xFC, 0x03, 0x03, 0x03, 0x03 }
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};
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/*static const u8 DDR2_ChB_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] =
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{
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// (And NOT) DDR800 DDR667 DDR533 DDR400
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//Reg Mask Value Value Value Value
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{0x74, 0x8F, 0x30, 0x40, 0x30, 0x20 }, // 1Rank
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{0x75, 0x8F, 0x30, 0x40, 0x30, 0x20 },
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{0x8A, 0x00, 0x10, 0x80, 0x07, 0x07 }
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};
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*/
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/*
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DQ/DQS Output Delay Control
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Modify NB D0F3: RxF0/RxF1/RxF2/RxF3
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*/
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static const u8 DDR2_CHA_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width] =
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{
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// RxF0 RxF1 RxF2 RxF3
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{ 0x00, 0x00, 0x00, 0x00 },// DDR400
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{ 0x00, 0x00, 0x00, 0x00 },// DDR533
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{ 0x00, 0x00, 0x00, 0x00 },// DDR667
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{ 0x00, 0x00, 0x00, 0x00 }// DDR800
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};
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static const u8 DDR2_CHB_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width] =
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{
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// RxF4 RxF5 RxF6 RxF7
|
||||
{ 0x00, 0x00, 0x00, 0x00 },// DDR400
|
||||
{ 0x00, 0x00, 0x00, 0x00 },// DDR533
|
||||
{ 0x00, 0x00, 0x00, 0x00 },// DDR667
|
||||
{ 0x00, 0x00, 0x00, 0x00 }// DDR800
|
||||
};
|
||||
|
||||
/*
|
||||
DQ/DQS input Capture Control
|
||||
modify NB D0F3_Reg:Rx78/Rx79/Rx7A/Rx7B
|
||||
*/
|
||||
//vt6413C
|
||||
/*static const u8 DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM] =
|
||||
{
|
||||
// (And NOT) DDR800 DDR667 DDR533 DDR400
|
||||
//Reg Mask Value Value Value Value
|
||||
{0x78, 0x00, 0x83, 0x8D, 0x87, 0x83 }, // 1Rank
|
||||
{0x7A, 0xF0, 0x00, 0x00, 0x00, 0x00 },
|
||||
{0x7B, 0x00, 0x10, 0x30, 0x20, 0x10 }
|
||||
};*/
|
||||
|
||||
//Vt6413D
|
||||
static const u8 DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM] =
|
||||
{
|
||||
// (And NOT) DDR800 DDR667 DDR533 DDR400
|
||||
//Reg Mask Value Value Value Value
|
||||
{0x78, 0xC0, 0x0D, 0x07, 0x03, 0x01 }, // 1Rank
|
||||
{0x7A, 0xF0, 0x00, 0x00, 0x00, 0x00 },
|
||||
{0x7B, 0x00, 0x34, 0x34, 0x20, 0x10 }
|
||||
};
|
||||
|
||||
static const u8 DDR2_ChB_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM] =
|
||||
{
|
||||
// (And NOT) DDR800 DDR667 DDR533 DDR400
|
||||
//Reg Mask Value Value Value Value
|
||||
{0x79, 0x00, 0x89, 0x89, 0x87, 0x83 }, // 1Rank
|
||||
{0x7A, 0x0F, 0x00, 0x00, 0x00, 0x00 },
|
||||
{0x8B, 0x00, 0x34, 0x34, 0x20, 0x10 }
|
||||
};
|
||||
|
||||
static const u8 Fixed_DQSA_1_2_Rank_Table[4][2] =
|
||||
{
|
||||
// Rx70 Rx71
|
||||
{ 0x00, 0x05 }, // DDR800
|
||||
{ 0x00, 0x06 }, // DDR667
|
||||
{ 0x00, 0x04 }, // DDR533
|
||||
{ 0x00, 0x05 } // DDR400
|
||||
static const u8 ChA_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM] = {
|
||||
// (And NOT) DDR800 DDR667 DDR533 DDR400
|
||||
//Reg Mask Value Value Value Value
|
||||
{0xEC, 0x00, 0x30, 0x30, 0x30, 0x30}, // 1Rank
|
||||
{0xEE, 0x0F, 0x40, 0x40, 0x00, 0x00},
|
||||
{0xEF, 0xCF, 0x00, 0x30, 0x30, 0x30},
|
||||
};
|
||||
static const u8 Fixed_DQSA_3_4_Rank_Table[4][2] =
|
||||
{
|
||||
// Rx70 Rx71
|
||||
{0x00 , 0x04}, // DDR800
|
||||
{0x00 , 0x04}, // DDR667
|
||||
{0x00 , 0x03}, // DDR533
|
||||
{0x00 , 0x04} // DDR400
|
||||
|
||||
static const u8 ChB_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM] = {
|
||||
// (And NOT) DDR800 DDR667 DDR533 DDR400
|
||||
//Reg Mask Value Value Value Value
|
||||
{0xED, 0x00, 0x88, 0x88, 0x84, 0x88}, // 1Rank
|
||||
{0xEE, 0xF0, 0x00, 0x00, 0x00, 0x00},
|
||||
{0xEF, 0xFC, 0x00, 0x00, 0x00, 0x00},
|
||||
};
|
||||
|
||||
/*
|
||||
* DRAM Clock Phase Control for FeedBack Mode
|
||||
* Modify NB Reg: Rx90[7]/Rx91/Rx92/Rx93/Rx94
|
||||
* Processing:
|
||||
* 1. Program VIA_NB3DRAM_REG90[7]=0b for FeedBack mode.
|
||||
* 2. Program clock phase value with ChA/B DCLK enable,
|
||||
* VIA_NB3DRAM_REG91[7:3]=00b
|
||||
* 3. Check ChB rank #, if 0, VIA_NB3DRAM_REG91[7]=1b, to disable ChB DCLKO
|
||||
* ChA DCLKO can't be disabled, so always program VIA_NB3DRAM_REG91[3]=0b.
|
||||
*/
|
||||
static const u8 DDR2_ChA_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width] = {
|
||||
// (And NOT) DDR800 DDR667 DDR533 DDR400
|
||||
//Reg Mask Value Value Value Value
|
||||
{0x91, 0xF8, 0x02, 0x01, 0x00, 0x07}, // 1Rank
|
||||
{0x92, 0xF8, 0x04, 0x03, 0x03, 0x02},
|
||||
{0x93, 0xF8, 0x06, 0x05, 0x04, 0x03},
|
||||
};
|
||||
|
||||
static const u8 DDR2_ChB_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width] = {
|
||||
// (And NOT) DDR800 DDR667 DDR533 DDR400
|
||||
//Reg Mask Value Value Value Value
|
||||
{0x91, 0x0F, 0x20, 0x10, 0x00, 0x70}, // 1Rank
|
||||
{0x92, 0x0F, 0x40, 0x30, 0x30, 0x20},
|
||||
{0x93, 0x0F, 0x60, 0x50, 0x40, 0x30},
|
||||
};
|
||||
|
||||
/* vt6413c */
|
||||
#if 0
|
||||
static const u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width] = {
|
||||
// (And NOT) DDR800 DDR667 DDR533 DDR400
|
||||
//Reg Mask Value Value Value Value
|
||||
{0x91, 0xF8, 0x04, 0x03, 0x04, 0x01 }, // 1Rank
|
||||
{0x92, 0xF8, 0x03, 0x06, 0x05, 0x04 },
|
||||
{0x93, 0xF8, 0x03, 0x07, 0x06, 0x05 },
|
||||
};
|
||||
#endif
|
||||
|
||||
/* vt6413d */
|
||||
static const u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width] = {
|
||||
// (And NOT) DDR800 DDR667 DDR533 DDR400
|
||||
//Reg Mask Value Value Value Value
|
||||
{0x91, 0xF8, 0x02, 0x01, 0x00, 0x07}, // 1Rank
|
||||
{0x92, 0xF8, 0x04, 0x03, 0x03, 0x02},
|
||||
{0x93, 0xF8, 0x06, 0x05, 0x04, 0x03},
|
||||
};
|
||||
|
||||
/*
|
||||
* DRAM Write Data phase control
|
||||
* Modify NB Reg: Rx74/Rx75/Rx76
|
||||
*/
|
||||
/* vt6413c */
|
||||
#if 0
|
||||
static const u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] = {
|
||||
// (And NOT) DDR800 DDR667 DDR533 DDR400
|
||||
//Reg Mask Value Value Value Value
|
||||
{0x74, 0xF8, 0x03, 0x04, 0x05, 0x02 }, // 1Rank
|
||||
{0x75, 0xF8, 0x03, 0x04, 0x05, 0x02 },
|
||||
{0x76, 0x00, 0x10, 0x80, 0x00, 0x07 },
|
||||
};
|
||||
#endif
|
||||
|
||||
/* vt6413D */
|
||||
static const u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM][WrtData_FREQ_NUM] = {
|
||||
// (And NOT) DDR800 DDR667 DDR533 DDR400
|
||||
//Reg Mask Value Value Value Value
|
||||
{0x74, 0xF8, 0x01, 0x00, 0x00, 0x07}, // 1Rank
|
||||
{0x75, 0xF8, 0x01, 0x00, 0x00, 0x07},
|
||||
{0x76, 0x10, 0x80, 0x87, 0x07, 0x06},
|
||||
{0x8C, 0xFC, 0x03, 0x03, 0x03, 0x03},
|
||||
};
|
||||
|
||||
#if 0
|
||||
static const u8 DDR2_ChB_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] = {
|
||||
// (And NOT) DDR800 DDR667 DDR533 DDR400
|
||||
//Reg Mask Value Value Value Value
|
||||
{0x74, 0x8F, 0x30, 0x40, 0x30, 0x20 }, // 1Rank
|
||||
{0x75, 0x8F, 0x30, 0x40, 0x30, 0x20 },
|
||||
{0x8A, 0x00, 0x10, 0x80, 0x07, 0x07 },
|
||||
};
|
||||
#endif
|
||||
|
||||
/*
|
||||
* DQ/DQS Output Delay Control
|
||||
* Modify NB D0F3: RxF0/RxF1/RxF2/RxF3
|
||||
*/
|
||||
static const u8 DDR2_CHA_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width] = {
|
||||
//RxF0 RxF1 RxF2 RxF3
|
||||
{0x00, 0x00, 0x00, 0x00}, /* DDR400 */
|
||||
{0x00, 0x00, 0x00, 0x00}, /* DDR533 */
|
||||
{0x00, 0x00, 0x00, 0x00}, /* DDR667 */
|
||||
{0x00, 0x00, 0x00, 0x00}, /* DDR800 */
|
||||
};
|
||||
|
||||
static const u8 DDR2_CHB_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width] = {
|
||||
//RxF4 RxF5 RxF6 RxF7
|
||||
{0x00, 0x00, 0x00, 0x00}, /* DDR400 */
|
||||
{0x00, 0x00, 0x00, 0x00}, /* DDR533 */
|
||||
{0x00, 0x00, 0x00, 0x00}, /* DDR667 */
|
||||
{0x00, 0x00, 0x00, 0x00}, /* DDR800 */
|
||||
};
|
||||
|
||||
/*
|
||||
* DQ/DQS input Capture Control
|
||||
* modify NB D0F3_Reg:Rx78/Rx79/Rx7A/Rx7B
|
||||
*/
|
||||
/* vt6413C */
|
||||
#if 0
|
||||
static const u8 DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM] = {
|
||||
// (And NOT) DDR800 DDR667 DDR533 DDR400
|
||||
//Reg Mask Value Value Value Value
|
||||
{0x78, 0x00, 0x83, 0x8D, 0x87, 0x83 }, // 1Rank
|
||||
{0x7A, 0xF0, 0x00, 0x00, 0x00, 0x00 },
|
||||
{0x7B, 0x00, 0x10, 0x30, 0x20, 0x10 }
|
||||
};
|
||||
#endif
|
||||
|
||||
/* vt6413D */
|
||||
static const u8DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM][DQS_INPUT_CAPTURE_FREQ_NUM] = {
|
||||
// (And NOT) DDR800 DDR667 DDR533 DDR400
|
||||
//Reg Mask Value Value Value Value
|
||||
{0x78, 0xC0, 0x0D, 0x07, 0x03, 0x01}, // 1Rank
|
||||
{0x7A, 0xF0, 0x00, 0x00, 0x00, 0x00},
|
||||
{0x7B, 0x00, 0x34, 0x34, 0x20, 0x10}
|
||||
};
|
||||
|
||||
static const u8 DDR2_ChB_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM][DQS_INPUT_CAPTURE_FREQ_NUM] = {
|
||||
// (And NOT) DDR800 DDR667 DDR533 DDR400
|
||||
//Reg Mask Value Value Value Value
|
||||
{0x79, 0x00, 0x89, 0x89, 0x87, 0x83}, // 1Rank
|
||||
{0x7A, 0x0F, 0x00, 0x00, 0x00, 0x00},
|
||||
{0x8B, 0x00, 0x34, 0x34, 0x20, 0x10}
|
||||
};
|
||||
|
||||
static const u8 Fixed_DQSA_1_2_Rank_Table[4][2] = {
|
||||
//Rx70 Rx71
|
||||
{0x00, 0x05}, /* DDR800 */
|
||||
{0x00, 0x06}, /* DDR667 */
|
||||
{0x00, 0x04}, /* DDR533 */
|
||||
{0x00, 0x05}, /* DDR400 */
|
||||
};
|
||||
|
||||
static const u8 Fixed_DQSA_3_4_Rank_Table[4][2] = {
|
||||
//Rx70 Rx71
|
||||
{0x00, 0x04}, /* DDR800 */
|
||||
{0x00, 0x04}, /* DDR667 */
|
||||
{0x00, 0x03}, /* DDR533 */
|
||||
{0x00, 0x04}, /* DDR400 */
|
||||
};
|
||||
|
|
|
|||
|
|
@ -67,11 +67,7 @@ uses TTYS0_BAUD
|
|||
uses CONFIG_VIDEO_MB
|
||||
uses CONFIG_IOAPIC
|
||||
|
||||
|
||||
|
||||
##
|
||||
## new options
|
||||
##
|
||||
## New options
|
||||
uses USE_DCACHE_RAM
|
||||
uses DCACHE_RAM_BASE
|
||||
uses DCACHE_RAM_SIZE
|
||||
|
|
@ -88,33 +84,31 @@ uses VIACONFIG_TOP_SM_SIZE_MB
|
|||
uses VIACONFIG_VGA_PCI_10
|
||||
uses VIACONFIG_VGA_PCI_14
|
||||
|
||||
##
|
||||
## new options
|
||||
##
|
||||
default USE_DCACHE_RAM=1
|
||||
default DCACHE_RAM_BASE=0xffef0000
|
||||
#default DCACHE_RAM_BASE=0xffbf0000
|
||||
#default DCACHE_RAM_BASE=0xfec00000 //hpet may use this
|
||||
default DCACHE_RAM_SIZE=0x2000
|
||||
default CONFIG_USE_INIT=0
|
||||
default MAX_RAM_SLOTS=2
|
||||
default USB_ENABLE=1
|
||||
default EHCI_ENABLE=1
|
||||
default HPET_ENABLE=1
|
||||
default USB_PORTNUM=2
|
||||
## New options
|
||||
default USE_DCACHE_RAM = 1
|
||||
default DCACHE_RAM_BASE = 0xffef0000
|
||||
# default DCACHE_RAM_BASE = 0xffbf0000
|
||||
# default DCACHE_RAM_BASE = 0xfec00000 # HPET may use this.
|
||||
default DCACHE_RAM_SIZE = 8 * 1024
|
||||
default CONFIG_USE_INIT = 0
|
||||
default MAX_RAM_SLOTS = 2
|
||||
default USB_ENABLE = 1
|
||||
default EHCI_ENABLE = 1
|
||||
default HPET_ENABLE = 1
|
||||
default USB_PORTNUM = 2
|
||||
default FULL_ROM_SIZE = 512 * 1024
|
||||
default FULL_ROM_BASE = (0xffffffff - FULL_ROM_SIZE+ 1)
|
||||
default VIACONFIG_TOP_SM_SIZE_MB=0
|
||||
#default VIACONFIG_VGA_PCI_10=0xd0000008
|
||||
#default VIACONFIG_VGA_PCI_14=0xfd000000
|
||||
default VIACONFIG_VGA_PCI_10=0xf8000008
|
||||
default VIACONFIG_VGA_PCI_14=0xfc000000
|
||||
|
||||
default FULL_ROM_BASE = (0xffffffff - FULL_ROM_SIZE + 1)
|
||||
default VIACONFIG_TOP_SM_SIZE_MB = 0
|
||||
# default VIACONFIG_VGA_PCI_10 = 0xd0000008
|
||||
# default VIACONFIG_VGA_PCI_14 = 0xfd000000
|
||||
default VIACONFIG_VGA_PCI_10 = 0xf8000008
|
||||
default VIACONFIG_VGA_PCI_14 = 0xfc000000
|
||||
|
||||
default ROM_SIZE = 512 * 1024
|
||||
default CONFIG_IOAPIC = 1
|
||||
|
||||
#define framebuffer size of VX800's integrated graphics card. support 32 64 128 256
|
||||
# Define framebuffer size of VX800's integrated graphics card.
|
||||
# Supports: 32, 64, 128, 256.
|
||||
default CONFIG_VIDEO_MB = 64
|
||||
|
||||
default CONFIG_CONSOLE_SERIAL8250 = 1
|
||||
|
|
@ -126,7 +120,7 @@ default CONFIG_UDELAY_TSC = 1
|
|||
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
|
||||
default HAVE_HARD_RESET = 0
|
||||
default HAVE_PIRQ_TABLE = 0
|
||||
default IRQ_SLOT_COUNT = 10
|
||||
default IRQ_SLOT_COUNT = 10 # FIXME. irq_table.c says 14.
|
||||
default HAVE_ACPI_TABLES = 1
|
||||
default HAVE_OPTION_TABLE = 1
|
||||
default ROM_IMAGE_SIZE = 128 * 1024
|
||||
|
|
@ -134,13 +128,14 @@ default FALLBACK_SIZE = ROM_SIZE
|
|||
default USE_FALLBACK_IMAGE = 1
|
||||
default STACK_SIZE = 16 * 1024
|
||||
default HEAP_SIZE = 20 * 1024
|
||||
#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
|
||||
# default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
|
||||
default USE_OPTION_TABLE = 0
|
||||
default _RAMBASE = 0x00004000
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
default CROSS_COMPILE = ""
|
||||
default CC = "$(CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC = "gcc"
|
||||
default CONFIG_CBFS = 0
|
||||
|
||||
##
|
||||
## Set this to the max PCI bus number you would ever use for PCI config I/O.
|
||||
|
|
@ -148,11 +143,5 @@ default HOSTCC = "gcc"
|
|||
## time when it can't find a device.
|
||||
##
|
||||
default CONFIG_MAX_PCI_BUSES = 3
|
||||
end
|
||||
|
||||
#
|
||||
# CBFS
|
||||
#
|
||||
#
|
||||
default CONFIG_CBFS=0
|
||||
end
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* LinuxBIOS ACPI Table support
|
||||
* written by Stefan Reinauer <stepan@openbios.org>
|
||||
* ACPI FADT, FACS, and DSDT table support added by
|
||||
* ACPI FADT, FACS, and DSDT table support added by
|
||||
* Nick Barker <nick.barker9@btinternet.com>, and those portions
|
||||
* (C) Copyright 2004 Nick Barker
|
||||
* (C) Copyright 2005 Stefan Reinauer
|
||||
|
|
@ -24,8 +24,8 @@
|
|||
*/
|
||||
|
||||
/*
|
||||
* most parts of this file copied from src\mainboard\asus\a8v-e_se\acpi_tables.c,
|
||||
* acpi_is_wakeup() is from Rudolf's S3 patch and SSDT was added
|
||||
* Most parts of this file copied from asus\a8v-e_se\acpi_tables.c,
|
||||
* acpi_is_wakeup() is from Rudolf's S3 patch and SSDT was added.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
|
|
@ -38,20 +38,24 @@
|
|||
extern unsigned char AmlCode_dsdt[];
|
||||
extern unsigned char AmlCode_ssdt[];
|
||||
|
||||
extern u32 wake_vec;
|
||||
extern u8 acpi_sleep_type;
|
||||
|
||||
/*
|
||||
These four macro copied from #include <arch/smp/mpspec.h>, I have to do this since "default HAVE_MP_TABLE = 0" in option.lb,
|
||||
and also since mainboard/via/*.* have no Mptable.c(so that I can not set HAVE_MP_TABLE = 1) as many other mainboard.
|
||||
So I have to copy these four to here. acpi_fill_madt() need this.
|
||||
*/
|
||||
* These four macros are copied from <arch/smp/mpspec.h>, I have to do this
|
||||
* since the "default HAVE_MP_TABLE = 0" in Options.lb, and also since
|
||||
* mainboard/via/... have no mptable.c (so that I can not set
|
||||
* HAVE_MP_TABLE = 1) as many other mainboards.
|
||||
* So I have to copy these four to here. acpi_fill_madt() needs this.
|
||||
*/
|
||||
#define MP_IRQ_POLARITY_HIGH 0x1
|
||||
#define MP_IRQ_POLARITY_LOW 0x3
|
||||
#define MP_IRQ_TRIGGER_EDGE 0x4
|
||||
#define MP_IRQ_TRIGGER_LEVEL 0xc
|
||||
|
||||
|
||||
unsigned long acpi_fill_mcfg(unsigned long current)
|
||||
{
|
||||
/* NO MCFG in VX855, no pci-e*/
|
||||
/* NO MCFG in VX855, no PCI-E. */
|
||||
return current;
|
||||
}
|
||||
|
||||
|
|
@ -60,34 +64,35 @@ unsigned long acpi_create_madt_lapics(unsigned long current)
|
|||
device_t cpu;
|
||||
int cpu_index = 0;
|
||||
|
||||
for(cpu = all_devices; cpu; cpu = cpu->next) {
|
||||
for (cpu = all_devices; cpu; cpu = cpu->next) {
|
||||
if ((cpu->path.type != DEVICE_PATH_APIC) ||
|
||||
(cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) {
|
||||
(cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) {
|
||||
continue;
|
||||
}
|
||||
if (!cpu->enabled) {
|
||||
if (!cpu->enabled)
|
||||
continue;
|
||||
}
|
||||
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, cpu_index, cpu->path.apic.apic_id);
|
||||
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current,
|
||||
cpu_index, cpu->path.apic.apic_id);
|
||||
cpu_index++;
|
||||
}
|
||||
return current;
|
||||
}
|
||||
|
||||
unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, u8 lint)
|
||||
unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags,
|
||||
u8 lint)
|
||||
{
|
||||
device_t cpu;
|
||||
int cpu_index = 0;
|
||||
|
||||
for(cpu = all_devices; cpu; cpu = cpu->next) {
|
||||
for (cpu = all_devices; cpu; cpu = cpu->next) {
|
||||
if ((cpu->path.type != DEVICE_PATH_APIC) ||
|
||||
(cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) {
|
||||
(cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) {
|
||||
continue;
|
||||
}
|
||||
if (!cpu->enabled) {
|
||||
if (!cpu->enabled)
|
||||
continue;
|
||||
}
|
||||
current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, cpu_index, flags, lint);
|
||||
current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
|
||||
current, cpu_index, flags, lint);
|
||||
cpu_index++;
|
||||
}
|
||||
return current;
|
||||
|
|
@ -102,11 +107,11 @@ unsigned long acpi_fill_madt(unsigned long current)
|
|||
|
||||
/* Write SB IOAPIC. */
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
|
||||
VX800SB_APIC_ID, VX800SB_APIC_BASE, 0);
|
||||
VX800SB_APIC_ID, VX800SB_APIC_BASE, 0);
|
||||
|
||||
/* IRQ0 -> APIC IRQ2. */
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 0, 2, 0x0);
|
||||
current, 0, 0, 2, 0x0);
|
||||
|
||||
/* IRQ9 ACPI active low. */
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
|
|
@ -114,20 +119,20 @@ unsigned long acpi_fill_madt(unsigned long current)
|
|||
|
||||
/* Create all subtables for processors. */
|
||||
current = acpi_create_madt_lapic_nmis(current,
|
||||
MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
|
||||
MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
|
||||
|
||||
return current;
|
||||
}
|
||||
|
||||
unsigned long acpi_fill_slit(unsigned long current)
|
||||
{
|
||||
// Not implemented
|
||||
return current;
|
||||
unsigned long acpi_fill_slit(unsigned long current)
|
||||
{
|
||||
/* Not implemented. */
|
||||
return current;
|
||||
}
|
||||
|
||||
|
||||
unsigned long acpi_fill_srat(unsigned long current)
|
||||
{
|
||||
/* No NUMA, no SRAT */
|
||||
/* No NUMA, no SRAT. */
|
||||
}
|
||||
|
||||
#define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1)
|
||||
|
|
@ -144,30 +149,27 @@ unsigned long write_acpi_tables(unsigned long start)
|
|||
acpi_madt_t *madt;
|
||||
acpi_fadt_t *fadt;
|
||||
acpi_facs_t *facs;
|
||||
acpi_header_t *dsdt;
|
||||
acpi_header_t *ssdt;
|
||||
|
||||
/* Align ACPI tables to 16byte */
|
||||
start = ( start + 0x0f ) & -0x10;
|
||||
acpi_header_t *dsdt, *ssdt;
|
||||
|
||||
/* Align ACPI tables to 16 byte. */
|
||||
start = (start + 0x0f) & -0x10;
|
||||
current = start;
|
||||
|
||||
|
||||
printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
|
||||
|
||||
/* We need at least an RSDP and an RSDT Table */
|
||||
/* We need at least an RSDP and an RSDT table. */
|
||||
rsdp = (acpi_rsdp_t *) current;
|
||||
current += sizeof(acpi_rsdp_t);
|
||||
rsdt = (acpi_rsdt_t *) current;
|
||||
current += sizeof(acpi_rsdt_t);
|
||||
|
||||
/* clear all table memory */
|
||||
/* Clear all table memory. */
|
||||
memset((void *)start, 0, current - start);
|
||||
|
||||
|
||||
acpi_write_rsdp(rsdp, rsdt);
|
||||
acpi_write_rsdt(rsdt);
|
||||
|
||||
/*
|
||||
* We explicitly add these tables later on:
|
||||
*/
|
||||
|
||||
/* We explicitly add these tables later on: */
|
||||
printk_debug("ACPI: * FACS\n");
|
||||
current = ALIGN(current, 64);
|
||||
facs = (acpi_facs_t *) current;
|
||||
|
|
@ -176,18 +178,19 @@ unsigned long write_acpi_tables(unsigned long start)
|
|||
|
||||
printk_debug("ACPI: * DSDT\n");
|
||||
dsdt = (acpi_header_t *) current;
|
||||
current += ((acpi_header_t *)AmlCode_dsdt)->length;
|
||||
memcpy((void *)dsdt,(void *)AmlCode_dsdt, ((acpi_header_t *)AmlCode_dsdt)->length);
|
||||
dsdt->checksum = 0; /* don't trust intel iasl compiler to get this right. */
|
||||
current += ((acpi_header_t *) AmlCode_dsdt)->length;
|
||||
memcpy((void *)dsdt, (void *)AmlCode_dsdt,
|
||||
((acpi_header_t *) AmlCode_dsdt)->length);
|
||||
dsdt->checksum = 0; /* Don't trust iasl to get this right. */
|
||||
dsdt->checksum = acpi_checksum(dsdt, dsdt->length);
|
||||
printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt, dsdt->length);
|
||||
|
||||
|
||||
printk_debug("ACPI: * FADT\n");
|
||||
fadt = (acpi_fadt_t *) current;
|
||||
current += sizeof(acpi_fadt_t);
|
||||
|
||||
acpi_create_fadt(fadt,facs,dsdt);
|
||||
acpi_add_table(rsdt,fadt);
|
||||
acpi_create_fadt(fadt, facs, dsdt);
|
||||
acpi_add_table(rsdt, fadt);
|
||||
|
||||
/* If we want to use HPET timers Linux wants it in MADT. */
|
||||
printk_debug("ACPI: * MADT\n");
|
||||
|
|
@ -195,33 +198,31 @@ unsigned long write_acpi_tables(unsigned long start)
|
|||
acpi_create_madt(madt);
|
||||
current += madt->header.length;
|
||||
acpi_add_table(rsdt, madt);
|
||||
|
||||
/* NO MCFG in VX855, no pci-e*/
|
||||
|
||||
/* NO MCFG in VX855, no PCI-E. */
|
||||
|
||||
printk_debug("ACPI: * HPET\n");
|
||||
hpet = (acpi_mcfg_t *) current;
|
||||
acpi_create_hpet(hpet);
|
||||
current += hpet->header.length;
|
||||
acpi_add_table(rsdt, hpet);
|
||||
/*
|
||||
|
||||
#if 0
|
||||
printk_debug("ACPI: * SSDT\n");
|
||||
ssdt = (acpi_header_t *) current;
|
||||
current += ((acpi_header_t *)AmlCode_ssdt)->length;
|
||||
memcpy((void *)ssdt,(void *)AmlCode_ssdt, ((acpi_header_t *)AmlCode_ssdt)->length);
|
||||
ssdt->checksum = 0; // don't trust intel iasl compiler to get this right
|
||||
ssdt->checksum = 0; /* Don't trust iasl to get this right. */
|
||||
ssdt->checksum = acpi_checksum(ssdt, ssdt->length);
|
||||
acpi_add_table(rsdt, ssdt);
|
||||
printk_debug("ACPI: * SSDT @ %08x Length %x\n", ssdt, ssdt->length);
|
||||
*/
|
||||
#endif
|
||||
|
||||
printk_info("ACPI: done.\n");
|
||||
return current;
|
||||
}
|
||||
|
||||
extern u32 wake_vec;
|
||||
extern u8 acpi_sleep_type;
|
||||
|
||||
int acpi_is_wakeup(void) {
|
||||
int acpi_is_wakeup(void)
|
||||
{
|
||||
return (acpi_sleep_type == 3);
|
||||
}
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -18,8 +18,7 @@
|
|||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
unsigned char AmlCode_dsdt[] =
|
||||
{
|
||||
0x44,0x53,0x44,0x54,0x0F,0x3C,0x00,0x00,
|
||||
unsigned char AmlCode_dsdt[] = {
|
||||
0x44, 0x53, 0x44, 0x54, 0x0F, 0x3C, 0x00, 0x00,
|
||||
/* Removed for lincense issue. See get_dsdt script. */
|
||||
};
|
||||
|
|
|
|||
|
|
@ -23,8 +23,9 @@
|
|||
#include <arch/acpi.h>
|
||||
#include <../../../northbridge/via/vx800/vx800.h>
|
||||
|
||||
void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
|
||||
acpi_header_t *header =& (fadt->header);
|
||||
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
|
||||
{
|
||||
acpi_header_t *header = &(fadt->header);
|
||||
|
||||
memset((void *)fadt, 0, sizeof(acpi_fadt_t));
|
||||
memcpy(header->signature, "FACP", 4);
|
||||
|
|
@ -40,54 +41,55 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
|
|||
fadt->preferred_pm_profile = 0;
|
||||
fadt->sci_int = 0x9;
|
||||
|
||||
fadt->smi_cmd = VX800_ACPI_IO_BASE+0x2F;
|
||||
fadt->smi_cmd = VX800_ACPI_IO_BASE + 0x2F;
|
||||
fadt->acpi_enable = 0xA1;
|
||||
fadt->acpi_disable = 0xA0;
|
||||
|
||||
/* value 42F,A1,A0, if we dont want SMI, then set them to zero.
|
||||
fadt->smi_cmd = 0x0;
|
||||
fadt->acpi_enable = 0x0;
|
||||
fadt->acpi_disable = 0x0;
|
||||
*/
|
||||
|
||||
/*
|
||||
* Value 42F,A1,A0, if we don't want SMI, then set them to zero.
|
||||
* fadt->smi_cmd = 0x0;
|
||||
* fadt->acpi_enable = 0x0;
|
||||
* fadt->acpi_disable = 0x0;
|
||||
*/
|
||||
|
||||
fadt->s4bios_req = 0x0;
|
||||
fadt->pstate_cnt = 0x0;
|
||||
|
||||
fadt->pm1a_evt_blk = VX800_ACPI_IO_BASE;
|
||||
fadt->pm1b_evt_blk = 0x0;
|
||||
fadt->pm1a_cnt_blk = VX800_ACPI_IO_BASE+0x4;
|
||||
fadt->pm1a_cnt_blk = VX800_ACPI_IO_BASE + 0x4;
|
||||
fadt->pm1b_cnt_blk = 0x0;
|
||||
fadt->pm2_cnt_blk = 0x22;//to support cpu-c3
|
||||
// fadt->pm2_cnt_blk = 0x0;
|
||||
fadt->pm_tmr_blk = VX800_ACPI_IO_BASE+0x8;
|
||||
fadt->gpe0_blk = VX800_ACPI_IO_BASE+0x20;
|
||||
fadt->gpe1_blk = VX800_ACPI_IO_BASE+0x50;
|
||||
fadt->pm2_cnt_blk = 0x22; /* To support cpu-c3. */
|
||||
/* fadt->pm2_cnt_blk = 0x0; */
|
||||
fadt->pm_tmr_blk = VX800_ACPI_IO_BASE + 0x8;
|
||||
fadt->gpe0_blk = VX800_ACPI_IO_BASE + 0x20;
|
||||
fadt->gpe1_blk = VX800_ACPI_IO_BASE + 0x50;
|
||||
|
||||
fadt->pm1_evt_len = 4;
|
||||
fadt->pm1_cnt_len = 2;
|
||||
fadt->pm2_cnt_len = 1;//to support cpu-c3
|
||||
// fadt->pm2_cnt_len = 0;
|
||||
fadt->pm2_cnt_len = 1; /* To support cpu-c3. */
|
||||
/* fadt->pm2_cnt_len = 0; */
|
||||
|
||||
fadt->pm_tmr_len = 4;
|
||||
fadt->gpe0_blk_len = 4;
|
||||
fadt->gpe1_blk_len = 4;
|
||||
fadt->gpe1_base = 0x10;
|
||||
fadt->cst_cnt = 0;
|
||||
|
||||
fadt->p_lvl2_lat = 0x50; //this is the coreboot source
|
||||
fadt->p_lvl3_lat = 0x320;//
|
||||
// fadt->p_lvl2_lat = 0x80; //
|
||||
// fadt->p_lvl3_lat = 0x800;//
|
||||
// fadt->p_lvl2_lat = 0x1; //
|
||||
// fadt->p_lvl3_lat = 0x23;
|
||||
|
||||
// fadt->p_lvl2_lat = 0x200; //disable
|
||||
// fadt->p_lvl3_lat = 0x2000;
|
||||
fadt->p_lvl2_lat = 0x50; /* This is the coreboot source. */
|
||||
fadt->p_lvl3_lat = 0x320;
|
||||
/* fadt->p_lvl2_lat = 0x80; */
|
||||
/* fadt->p_lvl3_lat = 0x800; */
|
||||
/* fadt->p_lvl2_lat = 0x1; */
|
||||
/* fadt->p_lvl3_lat = 0x23; */
|
||||
|
||||
/* fadt->p_lvl2_lat = 0x200; */ /* Disable. */
|
||||
/* fadt->p_lvl3_lat = 0x2000; */
|
||||
|
||||
fadt->flush_size = 0;
|
||||
fadt->flush_stride = 0;
|
||||
fadt->duty_offset = 0;
|
||||
// fadt->duty_width = 1;
|
||||
/* fadt->duty_width = 1; */
|
||||
fadt->duty_width = 4;
|
||||
fadt->day_alrm = 0x7d;
|
||||
fadt->mon_alrm = 0x7e;
|
||||
|
|
@ -126,7 +128,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
|
|||
fadt->x_pm1a_cnt_blk.bit_width = 2;
|
||||
fadt->x_pm1a_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm1a_cnt_blk.resv = 0;
|
||||
fadt->x_pm1a_cnt_blk.addrl = VX800_ACPI_IO_BASE+0x4;
|
||||
fadt->x_pm1a_cnt_blk.addrl = VX800_ACPI_IO_BASE + 0x4;
|
||||
fadt->x_pm1a_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1b_cnt_blk.space_id = 1;
|
||||
|
|
@ -136,8 +138,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
|
|||
fadt->x_pm1b_cnt_blk.addrl = 0x0;
|
||||
fadt->x_pm1b_cnt_blk.addrh = 0x0;
|
||||
|
||||
|
||||
// fadt->x_pm2_cnt_blk.space_id = 1;
|
||||
/* fadt->x_pm2_cnt_blk.space_id = 1; */
|
||||
fadt->x_pm2_cnt_blk.space_id = 0;
|
||||
fadt->x_pm2_cnt_blk.bit_width = 0;
|
||||
fadt->x_pm2_cnt_blk.bit_offset = 0;
|
||||
|
|
@ -149,14 +150,14 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
|
|||
fadt->x_pm_tmr_blk.bit_width = 4;
|
||||
fadt->x_pm_tmr_blk.bit_offset = 0;
|
||||
fadt->x_pm_tmr_blk.resv = 0;
|
||||
fadt->x_pm_tmr_blk.addrl = VX800_ACPI_IO_BASE+0x8;
|
||||
fadt->x_pm_tmr_blk.addrl = VX800_ACPI_IO_BASE + 0x8;
|
||||
fadt->x_pm_tmr_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_gpe0_blk.space_id = 1;
|
||||
fadt->x_gpe0_blk.bit_width = 0;
|
||||
fadt->x_gpe0_blk.bit_offset = 0;
|
||||
fadt->x_gpe0_blk.resv = 0;
|
||||
fadt->x_gpe0_blk.addrl = VX800_ACPI_IO_BASE+0x20;
|
||||
fadt->x_gpe0_blk.addrl = VX800_ACPI_IO_BASE + 0x20;
|
||||
fadt->x_gpe0_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_gpe1_blk.space_id = 1;
|
||||
|
|
|
|||
|
|
@ -19,25 +19,25 @@
|
|||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
# Simple script to dump the factory ACPI DSDT and convert it to C
|
||||
# Needs to be run as root on some systems, and always run on the target machine
|
||||
# Simple script to dump the factory ACPI DSDT and convert it to C.
|
||||
# Must be run as root on some systems, and always run on the target machine.
|
||||
|
||||
if [ ! iasl ]
|
||||
then echo "Intel ASL Compiler required to recompile DSDT table"
|
||||
if [ ! iasl ]; then
|
||||
echo "Intel ASL Compiler required to recompile DSDT table."
|
||||
fi
|
||||
|
||||
if [ ! -f /proc/acpi/dsdt ]
|
||||
then echo "Cannot find DSDT table, check that your kernel supports and uses ACPI"
|
||||
if [ ! -f /proc/acpi/dsdt ]; then
|
||||
echo "Cannot find DSDT table, check that your kernel supports and uses ACPI."
|
||||
fi
|
||||
|
||||
cat /proc/acpi/dsdt > dsdt
|
||||
if [ ! -f dsdt ]
|
||||
then echo "Failed copying DSDT, please check your permissions"
|
||||
if [ ! -f dsdt ]; then
|
||||
echo "Failed copying DSDT, please check your permissions."
|
||||
fi
|
||||
|
||||
iasl -d -vr -vs dsdt
|
||||
iasl -tc -vr -vs dsdt.dsl
|
||||
mv dsdt.hex dsdt.c
|
||||
echo "Done, cleaning up"
|
||||
echo "Done, cleaning up."
|
||||
rm -f dsdt dsdt.dsl dsdt.aml dsdt.hex
|
||||
exit
|
||||
|
|
|
|||
|
|
@ -18,41 +18,35 @@
|
|||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifdef GETPIR
|
||||
#include "pirq_routing.h"
|
||||
#else
|
||||
#include <arch/pirq_routing.h>
|
||||
#endif
|
||||
|
||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32+16*14, /* There can be total 14 devices on the bus */
|
||||
0x00, /* Where the interrupt router lies (bus) */
|
||||
(0x11<<3)|0x0, /* Where the interrupt router lies (dev) */
|
||||
0xc20, /* IRQs devoted exclusively to PCI usage */
|
||||
0x1106, /* Vendor */
|
||||
0x8409, /* Device */
|
||||
0, /* Crap (miniport) */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0xc6, /* u8 checksum. This has to be set to some
|
||||
//0xa0?? value that would give 0 after the sum of all
|
||||
bytes for this structure (including checksum) */
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32 + 16 * 14, /* There can be total 14 devices on the bus */
|
||||
0x00, /* Where the interrupt router lies (bus) */
|
||||
(0x11 << 3) | 0x0, /* Where the interrupt router lies (dev) */
|
||||
0xc20, /* IRQs devoted exclusively to PCI usage */
|
||||
0x1106, /* Vendor */
|
||||
0x8409, /* Device */
|
||||
0, /* Miniport */
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
|
||||
0xc6, /* Checksum. 0xa0? */
|
||||
{
|
||||
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
{0x00,(0x01<<3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
|
||||
{0x00,(0x08<<3)|0x0, {{0x01, 0xdeb8}, {0x01, 0xdeb8}, {0x01, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0},
|
||||
{0x00,(0x0b<<3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
|
||||
{0x00,(0x0c<<3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
|
||||
{0x00,(0x0d<<3)|0x0, {{0x02, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
|
||||
{0x00,(0x0e<<3)|0x0, {{0x03, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
|
||||
{0x00,(0x0f<<3)|0x0, {{0x02, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
|
||||
{0x00,(0x10<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0},
|
||||
{0x00,(0x14<<3)|0x0, {{0x02, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
|
||||
/* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
{0x00, (0x01 << 3) | 0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
|
||||
{0x00, (0x08 << 3) | 0x0, {{0x01, 0xdeb8}, {0x01, 0xdeb8}, {0x01, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0},
|
||||
{0x00, (0x0b << 3) | 0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
|
||||
{0x00, (0x0c << 3) | 0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
|
||||
{0x00, (0x0d << 3) | 0x0, {{0x02, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
|
||||
{0x00, (0x0e << 3) | 0x0, {{0x03, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
|
||||
{0x00, (0x0f << 3) | 0x0, {{0x02, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
|
||||
{0x00, (0x10 << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0},
|
||||
{0x00, (0x14 << 3) | 0x0, {{0x02, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
|
||||
}
|
||||
};
|
||||
|
||||
inline unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr);
|
||||
return copy_pirq_routing_table(addr);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -18,8 +18,7 @@
|
|||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
unsigned char AmlCode_ssdt[] =
|
||||
{
|
||||
0x53,0x53,0x44,0x54,0xA7,0x01,0x00,0x00, /* 00000000 "SSDT...." */
|
||||
unsigned char AmlCode_ssdt[] = {
|
||||
0x53, 0x53, 0x44, 0x54, 0xA7, 0x01, 0x00, 0x00,
|
||||
/* Removed for licese issue. */
|
||||
};
|
||||
|
|
|
|||
|
|
@ -19,208 +19,206 @@
|
|||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
//reboot.c from linux
|
||||
/*this file mostly copied from Rudolf's S3 patch, some changes in acpi_jump_wake()*/
|
||||
/* reboot.c from Linux. */
|
||||
|
||||
/*
|
||||
* This file mostly copied from Rudolf's S3 patch, some changes in
|
||||
* acpi_jump_wake().
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <arch/io.h>
|
||||
#include <console/console.h>
|
||||
#include <delay.h>
|
||||
#include <part/init_timer.h>//for jaon_tsc_count_end
|
||||
#include <part/init_timer.h> /* for jason_tsc_count_end */
|
||||
#include "wakeup.h"
|
||||
|
||||
|
||||
|
||||
|
||||
int enable_a20(void);
|
||||
|
||||
/* The following code and data reboots the machine by switching to real
|
||||
mode and jumping to the BIOS reset entry point, as if the CPU has
|
||||
really been reset. The previous version asked the keyboard
|
||||
controller to pulse the CPU reset line, which is more thorough, but
|
||||
doesn't work with at least one type of 486 motherboard. It is easy
|
||||
to stop this code working; hence the copious comments. */
|
||||
/*
|
||||
* The following code and data reboots the machine by switching to real
|
||||
* mode and jumping to the BIOS reset entry point, as if the CPU has
|
||||
* really been reset. The previous version asked the keyboard
|
||||
* controller to pulse the CPU reset line, which is more thorough, but
|
||||
* doesn't work with at least one type of 486 motherboard. It is easy
|
||||
* to stop this code working; hence the copious comments.
|
||||
*/
|
||||
|
||||
static unsigned long long
|
||||
real_mode_gdt_entries [3] =
|
||||
{
|
||||
static unsigned long long real_mode_gdt_entries[3] = {
|
||||
0x0000000000000000ULL, /* Null descriptor */
|
||||
0x00009a000000ffffULL, /* 16-bit real-mode 64k code at 0x00000000 */
|
||||
0x000092000100ffffULL /* 16-bit real-mode 64k data at 0x00000100 */
|
||||
};
|
||||
|
||||
struct Xgt_desc_struct {
|
||||
unsigned short size;
|
||||
unsigned long address __attribute__((packed));
|
||||
unsigned short pad;
|
||||
} __attribute__ ((packed));
|
||||
unsigned short size;
|
||||
unsigned long address __attribute__ ((packed));
|
||||
unsigned short pad;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
static struct Xgt_desc_struct
|
||||
real_mode_gdt = { sizeof (real_mode_gdt_entries) - 1, (long)real_mode_gdt_entries },
|
||||
real_mode_idt = { 0x3ff, 0 },
|
||||
no_idt = { 0, 0 };
|
||||
real_mode_gdt =
|
||||
{ sizeof(real_mode_gdt_entries) - 1, (long)real_mode_gdt_entries },
|
||||
real_mode_idt = {
|
||||
0x3ff, 0}, no_idt = {
|
||||
0, 0};
|
||||
|
||||
/*
|
||||
* This is 16-bit protected mode code to disable paging and the cache,
|
||||
* switch to real mode and jump to the BIOS reset code.
|
||||
*
|
||||
* The instruction that switches to real mode by writing to CR0 must be
|
||||
* followed immediately by a far jump instruction, which set CS to a
|
||||
* valid value for real mode, and flushes the prefetch queue to avoid
|
||||
* running instructions that have already been decoded in protected
|
||||
* mode.
|
||||
*
|
||||
* Clears all the flags except ET, especially PG (paging), PE
|
||||
* (protected-mode enable) and TS (task switch for coprocessor state
|
||||
* save). Flushes the TLB after paging has been disabled. Sets CD and
|
||||
* NW, to disable the cache on a 486, and invalidates the cache. This
|
||||
* is more like the state of a 486 after reset. I don't know if
|
||||
* something else should be done for other chips.
|
||||
*
|
||||
* More could be done here to set up the registers as if a CPU reset had
|
||||
* occurred; hopefully real BIOSs don't assume much.
|
||||
*/
|
||||
|
||||
/* This is 16-bit protected mode code to disable paging and the cache,
|
||||
switch to real mode and jump to the BIOS reset code.
|
||||
// 0x66, 0x0d, 0x00, 0x00, 0x00, 0x60, /* orl $0x60000000,%eax */
|
||||
|
||||
The instruction that switches to real mode by writing to CR0 must be
|
||||
followed immediately by a far jump instruction, which set CS to a
|
||||
valid value for real mode, and flushes the prefetch queue to avoid
|
||||
running instructions that have already been decoded in protected
|
||||
mode.
|
||||
|
||||
Clears all the flags except ET, especially PG (paging), PE
|
||||
(protected-mode enable) and TS (task switch for coprocessor state
|
||||
save). Flushes the TLB after paging has been disabled. Sets CD and
|
||||
NW, to disable the cache on a 486, and invalidates the cache. This
|
||||
is more like the state of a 486 after reset. I don't know if
|
||||
something else should be done for other chips.
|
||||
|
||||
More could be done here to set up the registers as if a CPU reset had
|
||||
occurred; hopefully real BIOSs don't assume much. */
|
||||
|
||||
|
||||
// 0x66, 0x0d, 0x00, 0x00, 0x00, 0x60, /* orl $0x60000000,%eax */
|
||||
|
||||
static unsigned char real_mode_switch [] =
|
||||
{
|
||||
0x66, 0x0f, 0x20, 0xc0, /* movl %cr0,%eax */
|
||||
0x24, 0xfe, /* andb $0xfe,al */
|
||||
0x66, 0x0f, 0x22, 0xc0 /* movl %eax,%cr0 */
|
||||
static unsigned char real_mode_switch[] = {
|
||||
0x66, 0x0f, 0x20, 0xc0, /* movl %cr0,%eax */
|
||||
0x24, 0xfe, /* andb $0xfe,al */
|
||||
0x66, 0x0f, 0x22, 0xc0 /* movl %eax,%cr0 */
|
||||
};
|
||||
static unsigned char jump_to_wakeup [] =
|
||||
{
|
||||
0xea, 0x00, 0x00, 0x00, 0xe0 /* ljmp $0xffff,$0x0000 */
|
||||
|
||||
static unsigned char jump_to_wakeup[] = {
|
||||
0xea, 0x00, 0x00, 0x00, 0xe0 /* ljmp $0xffff, $0x0000 */
|
||||
};
|
||||
|
||||
/*
|
||||
* Switch to real mode and then execute the code
|
||||
* specified by the code and length parameters.
|
||||
* We assume that length will aways be less that 100!
|
||||
*/
|
||||
static unsigned char show31 [6] =
|
||||
{
|
||||
0xb0, 0x31, 0xe6, 0x80, 0xeb ,0xFA /* ljmp $0xffff,$0x0000 */
|
||||
};
|
||||
static unsigned char show32 [6] =
|
||||
{
|
||||
0xb0, 0x32, 0xe6, 0x80, 0xeb ,0xFA /* ljmp $0xffff,$0x0000 */
|
||||
};
|
||||
*/
|
||||
static unsigned char show31[6] = {
|
||||
0xb0, 0x31, 0xe6, 0x80, 0xeb, 0xFA /* ljmp $0xffff,$0x0000 */
|
||||
};
|
||||
|
||||
static unsigned char show32[6] = {
|
||||
0xb0, 0x32, 0xe6, 0x80, 0xeb, 0xFA /* ljmp $0xffff,$0x0000 */
|
||||
};
|
||||
|
||||
void acpi_jump_wake(u32 vector)
|
||||
{
|
||||
u32 tmp;
|
||||
u16 tmpvector;
|
||||
u32 dwEip;
|
||||
u8 Data;
|
||||
struct Xgt_desc_struct * wake_thunk16_Xgt_desc;
|
||||
u32 tmp;
|
||||
u16 tmpvector;
|
||||
u32 dwEip;
|
||||
u8 Data;
|
||||
struct Xgt_desc_struct *wake_thunk16_Xgt_desc;
|
||||
|
||||
printk_debug("IN ACPI JUMP WAKE TO %x\n", vector);
|
||||
if (enable_a20())
|
||||
die("failed to enable A20\n");
|
||||
printk_debug("IN ACPI JUMP WAKE TO 3 %x\n", vector);
|
||||
|
||||
* ((u16 *) (jump_to_wakeup+3)) = (u16)(vector>>4);
|
||||
printk_debug("%x %x %x %x %x\n", jump_to_wakeup[0], jump_to_wakeup[1], jump_to_wakeup[2], jump_to_wakeup[3],jump_to_wakeup[4]);
|
||||
|
||||
memcpy ((void *) (WAKE_THUNK16_ADDR - sizeof (real_mode_switch) - 100),
|
||||
real_mode_switch, sizeof (real_mode_switch));
|
||||
memcpy ((void *) (WAKE_THUNK16_ADDR - 100), jump_to_wakeup, sizeof(jump_to_wakeup));
|
||||
*((u16 *) (jump_to_wakeup + 3)) = (u16) (vector >> 4);
|
||||
printk_debug("%x %x %x %x %x\n", jump_to_wakeup[0], jump_to_wakeup[1],
|
||||
jump_to_wakeup[2], jump_to_wakeup[3], jump_to_wakeup[4]);
|
||||
|
||||
memcpy((void *)(WAKE_THUNK16_ADDR - sizeof(real_mode_switch) - 100),
|
||||
real_mode_switch, sizeof(real_mode_switch));
|
||||
memcpy((void *)(WAKE_THUNK16_ADDR - 100), jump_to_wakeup,
|
||||
sizeof(jump_to_wakeup));
|
||||
|
||||
jason_tsc_count();
|
||||
printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
|
||||
printk_emerg("file '%s', line %d\n\n", __FILE__, __LINE__);
|
||||
jason_tsc_count_end();
|
||||
|
||||
unsigned long long *real_mode_gdt_entries_at_eseg;
|
||||
real_mode_gdt_entries_at_eseg = WAKE_THUNK16_GDT; //copy from real_mode_gdt_entries and change limition to 1M and data base to 0;
|
||||
real_mode_gdt_entries_at_eseg[0] = 0x0000000000000000ULL; /* Null descriptor */
|
||||
real_mode_gdt_entries_at_eseg[1] = 0x000f9a000000ffffULL; /* 16-bit real-mode 1M code at 0x00000000 */
|
||||
real_mode_gdt_entries_at_eseg[2] = 0x000f93000000ffffULL; /* 16-bit real-mode 1M data at 0x00000000 */
|
||||
|
||||
unsigned long long * real_mode_gdt_entries_at_eseg;
|
||||
real_mode_gdt_entries_at_eseg=WAKE_THUNK16_GDT; //copy from real_mode_gdt_entries and change limition to 1M and data base to 0;
|
||||
real_mode_gdt_entries_at_eseg [0] = 0x0000000000000000ULL; /* Null descriptor */
|
||||
real_mode_gdt_entries_at_eseg [1] = 0x000f9a000000ffffULL; /* 16-bit real-mode 1M code at 0x00000000 */
|
||||
real_mode_gdt_entries_at_eseg [2] = 0x000f93000000ffffULL; /* 16-bit real-mode 1M data at 0x00000000 */
|
||||
wake_thunk16_Xgt_desc = WAKE_THUNK16_XDTR;
|
||||
wake_thunk16_Xgt_desc[0].size = sizeof(real_mode_gdt_entries) - 1;
|
||||
wake_thunk16_Xgt_desc[0].address = (long)real_mode_gdt_entries_at_eseg;
|
||||
wake_thunk16_Xgt_desc[1].size = 0x3ff;
|
||||
wake_thunk16_Xgt_desc[1].address = 0;
|
||||
wake_thunk16_Xgt_desc[2].size = 0;
|
||||
wake_thunk16_Xgt_desc[2].address = 0;
|
||||
|
||||
wake_thunk16_Xgt_desc=WAKE_THUNK16_XDTR;
|
||||
wake_thunk16_Xgt_desc[0].size=sizeof (real_mode_gdt_entries) - 1;
|
||||
wake_thunk16_Xgt_desc[0].address=(long)real_mode_gdt_entries_at_eseg;
|
||||
wake_thunk16_Xgt_desc[1].size=0x3ff;
|
||||
wake_thunk16_Xgt_desc[1].address=0;
|
||||
wake_thunk16_Xgt_desc[2].size=0;
|
||||
wake_thunk16_Xgt_desc[2].address=0;
|
||||
|
||||
/*added this code to get current value of EIP
|
||||
*/
|
||||
__asm__ volatile (
|
||||
"calll geip\n\t"
|
||||
"geip: \n\t"
|
||||
"popl %0\n\t"
|
||||
:"=a"(dwEip)
|
||||
);
|
||||
/*added this code to get current value of EIP
|
||||
*/
|
||||
__asm__ volatile ("calll geip\n\t"
|
||||
"geip: \n\t" "popl %0\n\t":"=a" (dwEip)
|
||||
);
|
||||
|
||||
unsigned char *dest;
|
||||
unsigned char *src;
|
||||
src= (unsigned char *)dwEip;
|
||||
dest=WAKE_RECOVER1M_CODE;
|
||||
src = (unsigned char *)dwEip;
|
||||
dest = WAKE_RECOVER1M_CODE;
|
||||
u32 i;
|
||||
for (i = 0; i < 0x200; i++)
|
||||
dest[i] = src[i];
|
||||
|
||||
__asm__ __volatile__ ("ljmp $0x0010,%0"//08 error
|
||||
:
|
||||
: "i" ((void *) (WAKE_RECOVER1M_CODE+0x20)));
|
||||
for (i = 0; i < 0x200; i++)
|
||||
dest[i] = src[i];
|
||||
|
||||
/*added 0x20 "nop" to make sure the ljmp will not jump then halt*/
|
||||
asm volatile("nop");
|
||||
asm volatile("nop");
|
||||
asm volatile("nop");
|
||||
asm volatile("nop");
|
||||
asm volatile("nop");
|
||||
asm volatile("nop");
|
||||
asm volatile("nop");
|
||||
asm volatile("nop");
|
||||
asm volatile("nop");
|
||||
asm volatile("nop");
|
||||
__asm__ __volatile__("ljmp $0x0010,%0" //08 error
|
||||
::"i"((void *)(WAKE_RECOVER1M_CODE + 0x20)));
|
||||
|
||||
asm volatile("nop");
|
||||
asm volatile("nop");
|
||||
asm volatile("nop");
|
||||
asm volatile("nop");
|
||||
asm volatile("nop");
|
||||
asm volatile("nop");
|
||||
asm volatile("nop");
|
||||
asm volatile("nop");
|
||||
asm volatile("nop");
|
||||
asm volatile("nop");
|
||||
|
||||
asm volatile("nop");
|
||||
asm volatile("nop");
|
||||
asm volatile("nop");
|
||||
asm volatile("nop");
|
||||
asm volatile("nop");
|
||||
asm volatile("nop");
|
||||
asm volatile("nop");
|
||||
asm volatile("nop");
|
||||
asm volatile("nop");
|
||||
asm volatile("nop");
|
||||
|
||||
/*added 0x20 "nop" to make sure the ljmp will not jump then halt */
|
||||
asm volatile ("nop");
|
||||
asm volatile ("nop");
|
||||
asm volatile ("nop");
|
||||
asm volatile ("nop");
|
||||
asm volatile ("nop");
|
||||
asm volatile ("nop");
|
||||
asm volatile ("nop");
|
||||
asm volatile ("nop");
|
||||
asm volatile ("nop");
|
||||
asm volatile ("nop");
|
||||
|
||||
asm volatile ("nop");
|
||||
asm volatile ("nop");
|
||||
asm volatile ("nop");
|
||||
asm volatile ("nop");
|
||||
asm volatile ("nop");
|
||||
asm volatile ("nop");
|
||||
asm volatile ("nop");
|
||||
asm volatile ("nop");
|
||||
asm volatile ("nop");
|
||||
asm volatile ("nop");
|
||||
|
||||
asm volatile ("nop");
|
||||
asm volatile ("nop");
|
||||
asm volatile ("nop");
|
||||
asm volatile ("nop");
|
||||
asm volatile ("nop");
|
||||
asm volatile ("nop");
|
||||
asm volatile ("nop");
|
||||
asm volatile ("nop");
|
||||
asm volatile ("nop");
|
||||
asm volatile ("nop");
|
||||
|
||||
__asm__ volatile (
|
||||
/* set new esp, maybe ebp should not equal to esp?,
|
||||
due to the variable in acpi_jump_wake?, anyway, this may be not a big problem.
|
||||
and I didnt clear the area (ef000+-0x200) to zero.
|
||||
*/
|
||||
"movl %0, %%ebp\n\t"
|
||||
"movl %0, %%esp\n\t"
|
||||
::"a"(WAKE_THUNK16_STACK)
|
||||
);
|
||||
|
||||
/* set new esp, maybe ebp should not equal to esp?,
|
||||
due to the variable in acpi_jump_wake?, anyway, this may be not a big problem.
|
||||
and I didnt clear the area (ef000+-0x200) to zero.
|
||||
*/
|
||||
"movl %0, %%ebp\n\t"
|
||||
"movl %0, %%esp\n\t"::"a" (WAKE_THUNK16_STACK)
|
||||
);
|
||||
|
||||
/* added this
|
||||
only "src" and "dest" use the new stack, and the esp maybe also used in resumevector
|
||||
*/
|
||||
#if PAYLOAD_IS_SEABIOS==1
|
||||
only "src" and "dest" use the new stack, and the esp maybe also used in resumevector
|
||||
*/
|
||||
#if PAYLOAD_IS_SEABIOS==1
|
||||
// WAKE_MEM_INFO inited in get_set_top_available_mem in tables.c
|
||||
src = (unsigned char *)((* (u32*)WAKE_MEM_INFO)- 64*1024-0x100000);
|
||||
dest = 0;
|
||||
for (i = 0; i < 0xa0000; i++)//if recovered 0-e0000, then when resume, before winxp turn on the desktop screen ,there is gray background which last 1sec.
|
||||
src =
|
||||
(unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - 0x100000);
|
||||
dest = 0;
|
||||
for (i = 0; i < 0xa0000; i++) //if recovered 0-e0000, then when resume, before winxp turn on the desktop screen ,there is gray background which last 1sec.
|
||||
dest[i] = src[i];
|
||||
/*__asm__ volatile (
|
||||
"movl %0, %%esi\n\t"
|
||||
|
|
@ -230,55 +228,57 @@ struct Xgt_desc_struct * wake_thunk16_Xgt_desc;
|
|||
"rep movsd\n\t"
|
||||
::"a"(src)
|
||||
);*/
|
||||
src = (unsigned char *)((* (u32*)WAKE_MEM_INFO)- 64*1024-0x100000+0xc0000);
|
||||
src =
|
||||
(unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - 0x100000 +
|
||||
0xc0000);
|
||||
//dest = 0xc0000;
|
||||
//for (i = 0; i < 0x20000; i++)
|
||||
// dest[i] = src[i];
|
||||
/* __asm__ volatile (
|
||||
"movl %0, %%esi\n\t"
|
||||
"movl $0xc0000, %%edi\n\t"
|
||||
"movl $0x20000, %%ecx\n\t"
|
||||
"shrl $2, %%ecx\n\t"
|
||||
"rep movsd\n\t"
|
||||
::"a"(src)
|
||||
);*/
|
||||
// dest[i] = src[i];
|
||||
/* __asm__ volatile (
|
||||
"movl %0, %%esi\n\t"
|
||||
"movl $0xc0000, %%edi\n\t"
|
||||
"movl $0x20000, %%ecx\n\t"
|
||||
"shrl $2, %%ecx\n\t"
|
||||
"rep movsd\n\t"
|
||||
::"a"(src)
|
||||
); */
|
||||
|
||||
src =
|
||||
(unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - 0x100000 +
|
||||
0xe0000 + WAKE_SPECIAL_SIZE);
|
||||
//dest = 0xf0000;
|
||||
//for (i = 0; i < 0x10000; i++)
|
||||
// dest[i] = src[i];
|
||||
__asm__ volatile ("movl %0, %%esi\n\t"
|
||||
"movl %1, %%edi\n\t"
|
||||
"movl %2, %%ecx\n\t"
|
||||
"shrl $2, %%ecx\n\t"
|
||||
"rep movsd\n\t"::"r" (src),
|
||||
"r"(0xe0000 + WAKE_SPECIAL_SIZE),
|
||||
"r"(0x10000 - WAKE_SPECIAL_SIZE)
|
||||
);
|
||||
|
||||
src = (unsigned char *)((* (u32*)WAKE_MEM_INFO)- 64*1024-0x100000+0xe0000+WAKE_SPECIAL_SIZE);
|
||||
//dest = 0xf0000;
|
||||
//for (i = 0; i < 0x10000; i++)
|
||||
// dest[i] = src[i];
|
||||
__asm__ volatile (
|
||||
"movl %0, %%esi\n\t"
|
||||
"movl %1, %%edi\n\t"
|
||||
"movl %2, %%ecx\n\t"
|
||||
"shrl $2, %%ecx\n\t"
|
||||
"rep movsd\n\t"
|
||||
::"r"(src),"r"(0xe0000+WAKE_SPECIAL_SIZE), "r"(0x10000-WAKE_SPECIAL_SIZE)
|
||||
);
|
||||
|
||||
src = (unsigned char *)((* (u32*)WAKE_MEM_INFO)- 64*1024-0x100000+0xf0000);
|
||||
//dest = 0xf0000;
|
||||
//for (i = 0; i < 0x10000; i++)
|
||||
// dest[i] = src[i];
|
||||
__asm__ volatile (
|
||||
"movl %0, %%esi\n\t"
|
||||
"movl $0xf0000, %%edi\n\t"
|
||||
"movl $0x10000, %%ecx\n\t"
|
||||
"shrl $2, %%ecx\n\t"
|
||||
"rep movsd\n\t"
|
||||
::"a"(src)
|
||||
);
|
||||
|
||||
asm volatile("wbinvd");
|
||||
src =
|
||||
(unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - 0x100000 +
|
||||
0xf0000);
|
||||
//dest = 0xf0000;
|
||||
//for (i = 0; i < 0x10000; i++)
|
||||
// dest[i] = src[i];
|
||||
__asm__ volatile ("movl %0, %%esi\n\t"
|
||||
"movl $0xf0000, %%edi\n\t"
|
||||
"movl $0x10000, %%ecx\n\t"
|
||||
"shrl $2, %%ecx\n\t" "rep movsd\n\t"::"a" (src)
|
||||
);
|
||||
|
||||
asm volatile ("wbinvd");
|
||||
#endif
|
||||
/* Set up the IDT for real mode. */
|
||||
asm volatile("lidt %0"::"m" (wake_thunk16_Xgt_desc[1]));
|
||||
|
||||
asm volatile ("lidt %0"::"m" (wake_thunk16_Xgt_desc[1]));
|
||||
|
||||
/* Set up a GDT from which we can load segment descriptors for real
|
||||
mode. The GDT is not used in real mode; it is just needed here to
|
||||
prepare the descriptors. */
|
||||
asm volatile("lgdt %0"::"m" (wake_thunk16_Xgt_desc[0]));
|
||||
asm volatile ("lgdt %0"::"m" (wake_thunk16_Xgt_desc[0]));
|
||||
|
||||
/* Load the data segment registers, and thus the descriptors ready for
|
||||
real mode. The base address of each segment is 0x100, 16 times the
|
||||
|
|
@ -286,22 +286,21 @@ struct Xgt_desc_struct * wake_thunk16_Xgt_desc;
|
|||
registers don't have to be reloaded after switching to real mode:
|
||||
the values are consistent for real mode operation already. */
|
||||
|
||||
__asm__ __volatile__ ("movl $0x0010,%%eax\n"
|
||||
"\tmovl %%eax,%%ds\n"
|
||||
"\tmovl %%eax,%%es\n"
|
||||
"\tmovl %%eax,%%fs\n"
|
||||
"\tmovl %%eax,%%gs\n"
|
||||
"\tmovl %%eax,%%ss" : : : "eax");
|
||||
__asm__ __volatile__("movl $0x0010,%%eax\n"
|
||||
"\tmovl %%eax,%%ds\n"
|
||||
"\tmovl %%eax,%%es\n"
|
||||
"\tmovl %%eax,%%fs\n"
|
||||
"\tmovl %%eax,%%gs\n" "\tmovl %%eax,%%ss":::"eax");
|
||||
|
||||
/* Jump to the 16-bit code that we copied earlier. It disables paging
|
||||
and the cache, switches to real mode, and jumps to the BIOS reset
|
||||
entry point. */
|
||||
|
||||
__asm__ __volatile__ ("ljmp $0x0008,%0"
|
||||
:
|
||||
: "i" ((void *) (WAKE_THUNK16_ADDR - sizeof (real_mode_switch) - 100)));
|
||||
}
|
||||
|
||||
__asm__
|
||||
__volatile__("ljmp $0x0008,%0"::"i"
|
||||
((void *)(WAKE_THUNK16_ADDR -
|
||||
sizeof(real_mode_switch) - 100)));
|
||||
}
|
||||
|
||||
/* -*- linux-c -*- ------------------------------------------------------- *
|
||||
*
|
||||
|
|
@ -357,24 +356,24 @@ static int a20_test(int loops)
|
|||
int ok = 0;
|
||||
int saved, ctr;
|
||||
|
||||
// set_fs(0x0000);
|
||||
// set_gs(0xffff);
|
||||
// set_fs(0x0000);
|
||||
// set_gs(0xffff);
|
||||
|
||||
saved = ctr = *((u32*) A20_TEST_ADDR);
|
||||
saved = ctr = *((u32 *) A20_TEST_ADDR);
|
||||
|
||||
while (loops--) {
|
||||
//wrfs32(++ctr, A20_TEST_ADDR);
|
||||
|
||||
*((u32*) A20_TEST_ADDR) = ++ctr;
|
||||
|
||||
|
||||
*((u32 *) A20_TEST_ADDR) = ++ctr;
|
||||
|
||||
udelay(1); /* Serialize and make delay constant */
|
||||
|
||||
ok = *((u32 *) A20_TEST_ADDR+0xffff0+0x10) ^ ctr;
|
||||
|
||||
ok = *((u32 *) A20_TEST_ADDR + 0xffff0 + 0x10) ^ ctr;
|
||||
if (ok)
|
||||
break;
|
||||
}
|
||||
|
||||
*((u32*) A20_TEST_ADDR) = saved;
|
||||
*((u32 *) A20_TEST_ADDR) = saved;
|
||||
return ok;
|
||||
}
|
||||
|
||||
|
|
@ -407,7 +406,7 @@ static void enable_a20_fast(void)
|
|||
u8 port_a;
|
||||
|
||||
port_a = inb(0x92); /* Configuration port A */
|
||||
port_a |= 0x02; /* Enable A20 */
|
||||
port_a |= 0x02; /* Enable A20 */
|
||||
port_a &= ~0x01; /* Do not reset machine */
|
||||
outb(port_a, 0x92);
|
||||
}
|
||||
|
|
@ -431,7 +430,7 @@ int enable_a20(void)
|
|||
/* Try enabling A20 through the keyboard controller */
|
||||
empty_8042();
|
||||
//if (a20_test_short())
|
||||
// return 0; /* BIOS worked, but with delayed reaction */
|
||||
// return 0; /* BIOS worked, but with delayed reaction */
|
||||
|
||||
enable_a20_kbc();
|
||||
if (a20_test_long())
|
||||
|
|
|
|||
|
|
@ -21,13 +21,13 @@
|
|||
#ifndef WAKEUP_H
|
||||
#define WAKEUP_H
|
||||
|
||||
#define WAKE_SPECIAL_AREA 0xE0000
|
||||
#define WAKE_SPECIAL_SIZE 0x1000
|
||||
#define WAKE_THUNK16_ADDR (WAKE_SPECIAL_AREA+0x200)
|
||||
#define WAKE_THUNK16_GDT (WAKE_SPECIAL_AREA+0x300)
|
||||
#define WAKE_THUNK16_XDTR (WAKE_SPECIAL_AREA+0x350)
|
||||
#define WAKE_MEM_INFO (WAKE_SPECIAL_AREA+0x400)
|
||||
#define WAKE_RECOVER1M_CODE (WAKE_SPECIAL_AREA+0x500)
|
||||
#define WAKE_THUNK16_STACK (WAKE_SPECIAL_AREA+0xf00)
|
||||
#define WAKE_SPECIAL_AREA 0xE0000
|
||||
#define WAKE_SPECIAL_SIZE 0x1000
|
||||
#define WAKE_THUNK16_ADDR (WAKE_SPECIAL_AREA + 0x200)
|
||||
#define WAKE_THUNK16_GDT (WAKE_SPECIAL_AREA + 0x300)
|
||||
#define WAKE_THUNK16_XDTR (WAKE_SPECIAL_AREA + 0x350)
|
||||
#define WAKE_MEM_INFO (WAKE_SPECIAL_AREA + 0x400)
|
||||
#define WAKE_RECOVER1M_CODE (WAKE_SPECIAL_AREA + 0x500)
|
||||
#define WAKE_THUNK16_STACK (WAKE_SPECIAL_AREA + 0xf00)
|
||||
|
||||
#endif /* WAKEUP_H */
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue