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rambi: handle single channel configs 

Some 1.5 boards have a single channel ram configuration.
Accomodate such configs.

BUG=chrome-os-partner:22865
BRANCH=None
TEST=Built and booted ChromeOS.

Change-Id: I513327e47b9211d2dd1ea960d7da671a3773cb91
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178340
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Tested-by: Bernie Thompson <bhthompson@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: http://review.coreboot.org/4983
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Aaron Durbin 2013-11-27 16:51:26 -06:00 committed by Kyösti Mälkki
parent 13d9341660
commit 100b14d12b
2 changed files with 19 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
src/mainboard/google/rambi/romstage.c
View File

@ -31,7 +31,12 @@
* 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz
* 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz
* 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz
* 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
* 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz
*/
static const uint32_t dual_channel_config =
(1 << 0) | (1 << 1) | (1 << 2) | (1 << 3);
#define SPD_SIZE 256
#define GPIO_SSUS_37_PAD 57
#define GPIO_SSUS_38_PAD 50
@ -43,7 +48,7 @@ static inline void disable_internal_pull(int pad)
write32(ssus_pconf0(pad), read32(ssus_pconf0(pad)) & pull_mask);
}
static void *get_spd_pointer(char *spd_file_content, int total_spds)
static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual)
{
int ram_id = 0;
@ -63,6 +68,10 @@ static void *get_spd_pointer(char *spd_file_content, int total_spds)
if (ram_id >= total_spds)
return NULL;
/* Single channel configs */
if (dual_channel_config & (1 << ram_id))
*dual = 1;
return &spd_file_content[SPD_SIZE * ram_id];
}
@ -70,6 +79,7 @@ void mainboard_romstage_entry(struct romstage_params *rp)
{
struct cbfs_file *spd_file;
void *spd_content;
int dual_channel = 0;
struct mrc_params mp = {
.mainboard = {
@ -84,9 +94,11 @@ void mainboard_romstage_entry(struct romstage_params *rp)
/* Both channels are always present. */
spd_content = get_spd_pointer(CBFS_SUBHEADER(spd_file),
ntohl(spd_file->len) / SPD_SIZE);
ntohl(spd_file->len) / SPD_SIZE,
&dual_channel);
mp.mainboard.dram_data[0] = spd_content;
mp.mainboard.dram_data[1] = spd_content;
if (dual_channel)
mp.mainboard.dram_data[1] = spd_content;
rp->mrc_params = &mp;
romstage_common(rp);

4
src/mainboard/google/rambi/spd/Makefile.inc
View File

@ -25,10 +25,14 @@ SPD_BIN = $(obj)/spd.bin
# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz
# 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz
# 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz
# 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
# 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz
SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125
SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125
SPD_SOURCES += hynix_1GiB_dimm_H5TC2G63FFR-PBA
SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125
SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)