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nb/intel/gm45: Use LAPIC udelay instead of custom version 

This change may slow down the raminit by maximum 200usec,
but reuses the lapic udelay definition.

Change-Id: I60a68f8a7911b257c0eecda96f7c5bf302bb51ed
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17152
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Arthur Heymans 2016-10-27 00:31:41 +02:00 committed by Martin Roth
parent 3cf2d9caf5
commit 10141c3006
5 changed files with 5 additions and 40 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/northbridge/intel/gm45/Kconfig
View File

@ -26,7 +26,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select VGA
select INTEL_EDID
select INTEL_GMA_ACPI
select UDELAY_TSC
select UDELAY_LAPIC
config CBFS_SIZE
hex

1
src/northbridge/intel/gm45/Makefile.inc
View File

@ -17,7 +17,6 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_GM45),y)
romstage-y += early_init.c
romstage-y += early_reset.c
romstage-y += delay.c
romstage-y += raminit.c
romstage-y += raminit_rcomp_calibration.c
romstage-y += raminit_receive_enable_calibration.c

10
src/northbridge/intel/gm45/delay.c
View File

@ -84,13 +84,3 @@ void udelay(const u32 us)
{
_udelay(us, 1, 0);
}
void ns100delay(const u32 ns100)
{
_udelay(ns100, 10, 0);
}
void udelay_from_reset(const u32 us)
{
_udelay(us, 1, 1);
}

24
src/northbridge/intel/gm45/delay.h
View File

@ -1,24 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 secunet Security Networks AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __NORTHBRIDGE_INTEL_GM45_DELAY_H__
#define __NORTHBRIDGE_INTEL_GM45_DELAY_H__
#include <delay.h>
void ns100delay(u32);
void udelay_from_reset(u32);
#endif /* __NORTHBRIDGE_INTEL_GM45_DELAY_H__ */

8
src/northbridge/intel/gm45/raminit.c
View File

@ -24,7 +24,7 @@
#include <spd.h>
#include <console/console.h>
#include <lib.h>
#include "delay.h"
#include <delay.h>
#include "gm45.h"
#include "chip.h"
@ -916,15 +916,15 @@ static void rcomp_initialization(const stepping_t stepping, const int sff)
static void dram_powerup(const int resume)
{
udelay_from_reset(200);
udelay(200);
MCHBAR32(CLKCFG_MCHBAR) = (MCHBAR32(CLKCFG_MCHBAR) & ~(1 << 3)) | (3 << 21);
if (!resume) {
MCHBAR32(0x1434) |= (1 << 10);
ns100delay(2);
udelay(1);
}
MCHBAR32(0x1434) |= (1 << 6);
if (!resume) {
ns100delay(1);
udelay(1);
MCHBAR32(0x1434) |= (1 << 9);
MCHBAR32(0x1434) &= ~(1 << 10);
udelay(500);