sb/intel/lynxpoint: Finalize ME in ramstage
Performing ME finalization in SMM does not seem to be required. Tested on Asrock B85M Pro4, ME still gets finalized successfully. Change-Id: I9fde40a54f3fb8da2fba46c531443fdd2e067077 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -30,7 +30,7 @@ ramstage-y += acpi.c
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ramstage-$(CONFIG_ELOG) += elog.c
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c pmutil.c
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smm-y += smihandler.c me.c pch.c
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smm-y += smihandler.c pch.c
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smm-y += pmutil.c usb_ehci.c usb_xhci.c
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bootblock-y += early_pch.c
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@ -28,7 +28,7 @@
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#include <vendorcode/google/chromeos/chromeos.h>
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/* Path that the BIOS should take based on ME state */
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static const char *const me_bios_path_values[] __unused = {
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static const char *const me_bios_path_values[] = {
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[ME_NORMAL_BIOS_PATH] = "Normal",
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[ME_S3WAKE_BIOS_PATH] = "S3 Wake",
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[ME_ERROR_BIOS_PATH] = "Error",
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@ -40,11 +40,6 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev);
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/* MMIO base address for MEI interface */
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static u8 *mei_base_address;
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#ifdef __SIMPLE_DEVICE__
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void intel_me_mbp_clear(pci_devfn_t dev);
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#else
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void intel_me_mbp_clear(struct device *dev);
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#endif
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static void mei_dump(void *ptr, int dword, int offset, const char *type)
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{
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@ -98,11 +93,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
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mei_dump(ptr, dword, offset, "WRITE");
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}
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#ifdef __SIMPLE_DEVICE__
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static inline void pci_read_dword_ptr(pci_devfn_t dev, void *ptr, int offset)
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#else
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static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)
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#endif
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{
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u32 dword = pci_read_config32(dev, offset);
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memcpy(ptr, &dword, sizeof(dword));
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@ -401,11 +392,7 @@ static inline int mei_sendrecv_mkhi(struct mkhi_header *mkhi,
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* mbp give up routine. This path is taken if hfs.mpb_rdy is 0 or the read
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* state machine on the BIOS end doesn't match the ME's state machine.
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*/
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#ifdef __SIMPLE_DEVICE__
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static void intel_me_mbp_give_up(pci_devfn_t dev)
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#else
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static void intel_me_mbp_give_up(struct device *dev)
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#endif
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{
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struct mei_csr csr;
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@ -421,11 +408,7 @@ static void intel_me_mbp_give_up(struct device *dev)
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* mbp clear routine. This will wait for the ME to indicate that
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* the MBP has been read and cleared.
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*/
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#ifdef __SIMPLE_DEVICE__
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void intel_me_mbp_clear(pci_devfn_t dev)
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#else
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void intel_me_mbp_clear(struct device *dev)
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#endif
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static void intel_me_mbp_clear(struct device *dev)
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{
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int count;
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struct me_hfs2 hfs2;
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@ -446,7 +429,7 @@ void intel_me_mbp_clear(struct device *dev)
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}
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}
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static void __unused me_print_fw_version(mbp_fw_version_name *vers_name)
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static void me_print_fw_version(mbp_fw_version_name *vers_name)
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{
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if (!vers_name) {
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printk(BIOS_ERR, "ME: mbp missing version report\n");
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@ -485,7 +468,7 @@ static int mkhi_get_fwcaps(mbp_mefwcaps *cap)
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}
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/* Get ME Firmware Capabilities */
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static void __unused me_print_fwcaps(mbp_mefwcaps *cap)
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static void me_print_fwcaps(mbp_mefwcaps *cap)
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{
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mbp_mefwcaps local_caps;
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if (!cap) {
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@ -512,7 +495,7 @@ static void __unused me_print_fwcaps(mbp_mefwcaps *cap)
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}
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/* Send END OF POST message to the ME */
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static int __unused mkhi_end_of_post(void)
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static int mkhi_end_of_post(void)
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{
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struct mkhi_header mkhi = {
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.group_id = MKHI_GROUP_ID_GEN,
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@ -531,14 +514,12 @@ static int __unused mkhi_end_of_post(void)
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return 0;
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}
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#ifdef __SIMPLE_DEVICE__
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void intel_me_finalize_smm(void)
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void intel_me_finalize(struct device *dev)
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{
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struct me_hfs hfs;
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u32 reg32;
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reg32 = pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0);
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reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
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mei_base_address = (u8 *)(uintptr_t)(reg32 & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK);
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/* S3 path will have hidden this device already */
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@ -546,10 +527,10 @@ void intel_me_finalize_smm(void)
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return;
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/* Wait for ME MBP Cleared indicator */
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intel_me_mbp_clear(PCH_ME_DEV);
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intel_me_mbp_clear(dev);
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/* Make sure ME is in a mode that expects EOP */
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reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS);
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reg32 = pci_read_config32(dev, PCI_ME_HFS);
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memcpy(&hfs, ®32, sizeof(u32));
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/* Abort and leave device alone if not normal mode */
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@ -562,15 +543,13 @@ void intel_me_finalize_smm(void)
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mkhi_end_of_post();
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/* Make sure IO is disabled */
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pci_and_config16(PCH_ME_DEV, PCI_COMMAND,
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pci_and_config16(dev, PCI_COMMAND,
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~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
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/* Hide the PCI device */
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RCBA32_OR(FD2, PCH_DISABLE_MEI1);
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}
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#else /* !__SIMPLE_DEVICE__ */
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static inline int mei_sendrecv_icc(struct icc_header *icc,
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void *req_data, int req_bytes,
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void *rsp_data, int rsp_bytes)
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@ -809,7 +788,7 @@ static void intel_me_init(struct device *dev)
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me_icc_set_clock_enables(config->icc_clock_disable);
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/*
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* Leave the ME unlocked. It will be locked via SMI command later.
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* Leave the ME unlocked. It will be locked later.
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*/
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}
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@ -828,6 +807,7 @@ static struct device_operations device_ops = {
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.enable_resources = pci_dev_enable_resources,
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.enable = intel_me_enable,
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.init = intel_me_init,
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.final = intel_me_finalize,
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.ops_pci = &pci_dev_ops_pci,
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};
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@ -843,8 +823,6 @@ static const struct pci_driver intel_me __pci_driver = {
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.devices = pci_device_ids,
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};
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#endif /* !__SIMPLE_DEVICE__ */
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/******************************************************************************
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* */
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static u32 me_to_host_words_pending(void)
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@ -866,7 +844,7 @@ struct mbp_payload {
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* mbp seems to be following its own flow, let's retrieve it in a dedicated
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* function.
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*/
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static int __unused intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev)
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static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev)
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{
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mbp_header mbp_hdr;
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u32 me2host_pending;
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@ -875,11 +853,7 @@ static int __unused intel_me_read_mbp(me_bios_payload *mbp_data, struct device *
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struct mbp_payload *mbp;
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int i;
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#ifdef __SIMPLE_DEVICE__
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pci_read_dword_ptr(PCI_BDF(dev), &hfs2, PCI_ME_HFS2);
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#else
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pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2);
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#endif
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if (!hfs2.mbp_rdy) {
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printk(BIOS_ERR, "ME: MBP not ready\n");
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@ -984,10 +958,6 @@ static int __unused intel_me_read_mbp(me_bios_payload *mbp_data, struct device *
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return 0;
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mbp_failure:
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#ifdef __SIMPLE_DEVICE__
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intel_me_mbp_give_up(PCI_BDF(dev));
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#else
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intel_me_mbp_give_up(dev);
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#endif
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return -1;
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}
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@ -317,8 +317,7 @@ int intel_early_me_init(void);
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int intel_early_me_uma_size(void);
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int intel_early_me_init_done(u8 status);
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void intel_me_finalize_smm(void);
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void intel_me8_finalize_smm(void);
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void intel_me_finalize(struct device *dev);
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/*
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* ME to BIOS Payload Datastructures and definitions. The ordering of the
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@ -272,7 +272,6 @@ static void southbridge_smi_apmc(void)
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return;
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}
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intel_me_finalize_smm();
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intel_pch_finalize_smm();
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intel_northbridge_haswell_finalize_smm();
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intel_cpu_haswell_finalize_smm();
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