mb/intel/wtm2: Drop unsupported native graphics init
Since the conversion of this board to soc/broadwell in 0aa06cbf18
(wtm2: Convert to use soc/intel/broadwell), the NGI for this board
is not hooked up anywhere. Also, the code doesn't compile anymore.
Change-Id: I6387203349b78c8e95333eaf44b345aa30eac7c5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Nico Huber
parent
bb72852baf
commit
10326ba889
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@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select HAVE_SMI_HANDLER
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_LPC_TPM
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select MAINBOARD_HAS_NATIVE_VGA_INIT
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select INTEL_INT15
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config CHROMEOS
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@ -15,9 +15,6 @@
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romstage-y += chromeos.c
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ramstage-y += chromeos.c
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ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915.c
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ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += graphics.c
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ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += intel_dp.c
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romstage-y += pei_data.c
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ramstage-y += pei_data.c
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@ -1,83 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* this file was for the most part machine generated, and in future
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* will be all machine generated. Avoid editing.
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*/
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#include <console/console.h>
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#include <drivers/intel/gma/i915.h>
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void graphics_register_reset(u32 aux_ctl, u32 aux_data, int verbose)
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{
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io_i915_write32(0x80000000,0x45400);
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io_i915_write32(0x00000000,_CURACNTR);
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io_i915_write32((/* PIPEA */0x0 << 24)|0x00000000,_DSPACNTR);
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io_i915_write32(0x00000000,_DSPBCNTR);
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io_i915_write32(0x80000000,CPU_VGACNTRL);
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io_i915_write32(0x00000000,_DSPASIZE+0xc);
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io_i915_write32(0x00000000,_DSPBSURF);
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io_i915_write32(0x00000000,0x4f050);
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io_i915_write32( DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT |
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DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 |
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DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE |
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DP_SYNC_VS_HIGH |0x00000091,DP_A);
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io_i915_write32(0x00200090,_FDI_RXA_MISC);
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io_i915_write32(0x0a000000,_FDI_RXA_MISC);
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/* not yet documented anywhere that we can find. */
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io_i915_write32(0x00000070,0x46408);
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io_i915_write32(0x04000000,0x42090);
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io_i915_write32(0x40000000,0x4f050);
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io_i915_write32(0x00000000,0x9840);
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io_i915_write32(0xa4000000,0x42090);
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io_i915_write32(0x00004000,0x42080);
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io_i915_write32(0x00ffffff,0x64f80);
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io_i915_write32(0x0007000e,0x64f84);
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io_i915_write32(0x00d75fff,0x64f88);
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io_i915_write32(0x000f000a,0x64f8c);
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io_i915_write32(0x00c30fff,0x64f90);
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io_i915_write32(0x00060006,0x64f94);
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io_i915_write32(0x00aaafff,0x64f98);
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io_i915_write32(0x001e0000,0x64f9c);
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io_i915_write32(0x00ffffff,0x64fa0);
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io_i915_write32(0x000f000a,0x64fa4);
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io_i915_write32(0x00d75fff,0x64fa8);
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io_i915_write32(0x00160004,0x64fac);
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io_i915_write32(0x00c30fff,0x64fb0);
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io_i915_write32(0x001e0000,0x64fb4);
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io_i915_write32(0x00ffffff,0x64fb8);
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io_i915_write32(0x00060006,0x64fbc);
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io_i915_write32(0x00d75fff,0x64fc0);
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io_i915_write32(0x001e0000,0x64fc4);
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io_i915_write32(0x00ffffff,0x64e00);
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io_i915_write32(0x0006000e,0x64e04);
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io_i915_write32(0x00d75fff,0x64e08);
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io_i915_write32(0x0005000a,0x64e0c);
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io_i915_write32(0x00c30fff,0x64e10);
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io_i915_write32(0x00040006,0x64e14);
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io_i915_write32(0x80aaafff,0x64e18);
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io_i915_write32(0x000b0000,0x64e1c);
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io_i915_write32(0x00ffffff,0x64e20);
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io_i915_write32(0x0005000a,0x64e24);
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io_i915_write32(0x00d75fff,0x64e28);
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io_i915_write32(0x000c0004,0x64e2c);
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io_i915_write32(0x80c30fff,0x64e30);
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io_i915_write32(0x000b0000,0x64e34);
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io_i915_write32(0x00ffffff,0x64e38);
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io_i915_write32(0x00040006,0x64e3c);
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io_i915_write32(0x80d75fff,0x64e40);
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io_i915_write32(0x000b0000,0x64e44);
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/* end not yet documented. */
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io_i915_write32(0x10000000,SDEISR+0x30);
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}
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@ -1,228 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <types.h>
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#include <string.h>
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#include <stdlib.h>
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#include <device/device.h>
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#include <device/device.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <console/console.h>
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#include <delay.h>
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#include <pc80/mc146818rtc.h>
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#include <arch/acpi.h>
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#include <arch/io.h>
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#include <arch/interrupt.h>
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#include <boot/coreboot_tables.h>
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#include <smbios.h>
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#include <device/pci.h>
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#include <ec/google/chromeec/ec.h>
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#include <cpu/x86/tsc.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/msr.h>
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#include <edid.h>
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#include <drivers/intel/gma/i915.h>
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/* how many bytes do we need for the framebuffer?
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* Well, this gets messy. To get an exact answer, we have
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* to ask the panel, but we'd rather zero the memory
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* and set up the gtt while the panel powers up. So,
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* we take a reasonable guess, secure in the knowledge that the
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* MRC has to overestimate the number of bytes used.
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* 8 MiB is a very safe guess. There may be a better way later, but
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* fact is, the initial framebuffer is only very temporary. And taking
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* a little long is ok; this is done much faster than the AUX
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* channel is ready for IO.
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*/
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#define FRAME_BUFFER_BYTES (8*MiB)
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/* how many 4096-byte pages do we need for the framebuffer?
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* There are hard ways to get this, and easy ways:
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* there are FRAME_BUFFER_BYTES/4096 pages, since pages are 4096
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* on this chip (and in fact every Intel graphics chip we've seen).
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*/
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#define FRAME_BUFFER_PAGES (FRAME_BUFFER_BYTES/(4096))
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static int verbose = 0;
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static unsigned int *mmio;
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static unsigned int graphics;
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static unsigned short addrport;
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static unsigned short dataport;
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static unsigned int physbase;
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const u32 link_edid_data[] = {
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0xffffff00, 0x00ffffff, 0x0379e430, 0x00000000,
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0x04011500, 0x96121ba5, 0xa2d54f02, 0x26935259,
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0x00545017, 0x01010000, 0x01010101, 0x01010101,
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0x01010101, 0x6f6d0101, 0xa4a0a000, 0x20306031,
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0xb510003a, 0x19000010, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x4c00fe00,
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0x69442047, 0x616c7073, 0x20200a79, 0xfe000000,
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0x31504c00, 0x45513932, 0x50532d31, 0x24003141,
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};
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static int ioread = 0, iowrite = 0;
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static char *regname(unsigned long addr)
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{
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static char name[16];
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snprintf(name, sizeof(name), "0x%lx", addr);
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return name;
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}
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unsigned long io_i915_read32(unsigned long addr)
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{
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unsigned long val;
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outl(addr, addrport);
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val = inl(dataport);
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ioread += 2;
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if (verbose & vio)printk(BIOS_SPEW, "%s: Got %08lx\n", regname(addr), val);
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return val;
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}
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void io_i915_write32(unsigned long val, unsigned long addr)
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{
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if (verbose & vio)printk(BIOS_SPEW, "%s: outl %08lx\n", regname(addr), val);
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outl(addr, addrport);
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outl(val, dataport);
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iowrite += 2;
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}
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/* GTT is the Global Translation Table for the graphics pipeline.
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* It is used to translate graphics addresses to physical
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* memory addresses. As in the CPU, GTTs map 4K pages.
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* The setgtt function adds a further bit of flexibility:
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* it allows you to set a range (the first two parameters) to point
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* to a physical address (third parameter);the physical address is
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* incremented by a count (fourth parameter) for each GTT in the
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* range.
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* Why do it this way? For ultrafast startup,
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* we can point all the GTT entries to point to one page,
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* and set that page to 0s:
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* memset(physbase, 0, 4096);
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* setgtt(0, 4250, physbase, 0);
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* this takes about 2 ms, and is a win because zeroing
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* the page takes a up to 200 ms.
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* This call sets the GTT to point to a linear range of pages
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* starting at physbase.
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*/
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static void
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setgtt(int start, int end, unsigned long base, int inc)
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{
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int i;
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for(i = start; i < end; i++){
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u32 word = base + i*inc;
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io_i915_write32(word|1,(i*4)|1);
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}
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}
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static unsigned long tickspermicrosecond = 1795;
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static unsigned long long globalstart;
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static unsigned long
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microseconds(unsigned long long start, unsigned long long end)
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{
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unsigned long ret;
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ret = ((end - start)/tickspermicrosecond);
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return ret;
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}
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static unsigned long globalmicroseconds(void)
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{
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return microseconds(globalstart, rdtscll());
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}
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static int i915_init_done = 0;
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int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio,
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unsigned int gfx);
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int i915lightup(unsigned int pphysbase, unsigned int piobase,
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unsigned int pmmio, unsigned int pgfx)
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{
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int must_cycle_power = 0;
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/* frame buffer pointer */
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u32 *l;
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int i;
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unsigned long before_gtt, after_gtt;
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mmio = (void *)pmmio;
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addrport = piobase;
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dataport = addrport + 4;
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physbase = pphysbase;
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graphics = pgfx;
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printk(BIOS_SPEW,
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"i915lightup: graphics %p mmio %p"
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"addrport %04x physbase %08x\n",
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(void *)graphics, mmio, addrport, physbase);
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globalstart = rdtscll();
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/* turn it on. The VBIOS does it this way, so we hope that's ok. */
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verbose = 0;
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io_i915_write32(0xabcd000f, PCH_PP_CONTROL);
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/* the AUX channel needs a small amount of time to spin up.
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* Rather than udelay, do some useful work:
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* Zero out the frame buffer memory,
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* and set the global translation table (GTT)
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*/
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printk(BIOS_SPEW, "Set not-White (%08x) for %d pixels\n", 0xffffff,
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FRAME_BUFFER_BYTES/sizeof(u32));
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for(l = (u32 *)graphics, i = 0;
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i < FRAME_BUFFER_BYTES/sizeof(u32); i++){
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l[i] = 0x1122ff;
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}
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printk(BIOS_SPEW, "GTT: set %d pages starting at %p\n",
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FRAME_BUFFER_PAGES, (void *)physbase);
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before_gtt = globalmicroseconds();
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setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096);
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after_gtt = globalmicroseconds();
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/* The reset is basically harmless, and can be
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* repeated by the VBIOS in any event.
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*/
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graphics_register_reset(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, verbose);
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/* failures after this point can return without
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* powering off the panel.
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*/
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if (1)
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goto fail;
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/* failures after this point MUST power off the panel
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* and wait 600 ms.
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*/
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i915_init_done = 1;
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return i915_init_done;
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fail:
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printk(BIOS_SPEW, "Graphics could not be started;");
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if (must_cycle_power){
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printk(BIOS_SPEW, "Turn off power and wait ...");
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io_i915_write32(0xabcd0000, PCH_PP_CONTROL);
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udelay(600000);
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}
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printk(BIOS_SPEW, "Returning.\n");
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return 0;
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}
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@ -1,167 +0,0 @@
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/*
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* Copyright 2013 Google Inc.
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* Copyright © 2008 Intel Corporation
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*
|
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*
|
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* Permission is hereby granted, free of charge, to any person obtaining a
|
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* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
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*
|
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* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
||||
* IN THE SOFTWARE.
|
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*
|
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* Authors:
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* Keith Packard <keithp@keithp.com>
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*
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*/
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|
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#include <console/console.h>
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#include <stdint.h>
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#include <delay.h>
|
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#include <drivers/intel/gma/i915.h>
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u32
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pack_aux(u32 *src32, int src_bytes)
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{
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u8 *src = (u8 *)src32;
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int i;
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u32 v = 0;
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if (src_bytes > 4)
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src_bytes = 4;
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for (i = 0; i < src_bytes; i++)
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v |= ((u32) src[i]) << ((3-i) * 8);
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return v;
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}
|
||||
|
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void
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unpack_aux(u32 src, u8 *dst, int dst_bytes)
|
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{
|
||||
|
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int i;
|
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if (dst_bytes > 4)
|
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dst_bytes = 4;
|
||||
for (i = 0; i < dst_bytes; i++)
|
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dst[i] = src >> ((3-i) * 8);
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}
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|
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int
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intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes,
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u8 *recv, int recv_size)
|
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{
|
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int i;
|
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int recv_bytes;
|
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u32 status;
|
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u32 aux_clock_divider;
|
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int try, precharge = 5;
|
||||
|
||||
/* The clock divider is based off the hrawclk,
|
||||
* and would like to run at 2MHz. So, take the
|
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* hrawclk value and divide by 2 and use that
|
||||
*
|
||||
* Note that PCH attached eDP panels should use a 125MHz input
|
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* clock divider.
|
||||
*/
|
||||
/* 200 on link */
|
||||
aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
|
||||
|
||||
/* Try to wait for any previous AUX channel activity */
|
||||
for (try = 0; try < 3; try++) {
|
||||
status = io_i915_read32(ch_ctl);
|
||||
if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
|
||||
break;
|
||||
udelay(1000);
|
||||
}
|
||||
|
||||
if (try == 3) {
|
||||
printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__);
|
||||
status = io_i915_read32(ch_ctl);
|
||||
printk(BIOS_SPEW, "dp_aux_ch not started status 0x%08x\n",
|
||||
status);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Must try at least 3 times according to DP spec */
|
||||
for (try = 0; try < 5; try++) {
|
||||
/* Load the send data into the aux channel data registers */
|
||||
for (i = 0; i < send_bytes; i += 4)
|
||||
io_i915_write32(send[i], ch_data + i);
|
||||
|
||||
/* Send the command and wait for it to complete */
|
||||
io_i915_write32(
|
||||
DP_AUX_CH_CTL_SEND_BUSY |
|
||||
DP_AUX_CH_CTL_TIME_OUT_400us |
|
||||
(send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
|
||||
(precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
|
||||
(aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
|
||||
DP_AUX_CH_CTL_DONE |
|
||||
DP_AUX_CH_CTL_TIME_OUT_ERROR |
|
||||
DP_AUX_CH_CTL_RECEIVE_ERROR, ch_ctl);
|
||||
for (;;) {
|
||||
status = io_i915_read32(ch_ctl);
|
||||
if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
|
||||
break;
|
||||
udelay(100);
|
||||
}
|
||||
|
||||
/* Clear done status and any errors */
|
||||
io_i915_write32(
|
||||
status |
|
||||
DP_AUX_CH_CTL_DONE |
|
||||
DP_AUX_CH_CTL_TIME_OUT_ERROR |
|
||||
DP_AUX_CH_CTL_RECEIVE_ERROR, ch_ctl);
|
||||
|
||||
if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
|
||||
DP_AUX_CH_CTL_RECEIVE_ERROR))
|
||||
continue;
|
||||
if (status & DP_AUX_CH_CTL_DONE)
|
||||
break;
|
||||
}
|
||||
|
||||
if ((status & DP_AUX_CH_CTL_DONE) == 0) {
|
||||
printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__);
|
||||
printk(BIOS_SPEW, "dp_aux_ch not done status 0x%08x\n", status);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Check for timeout or receive error.
|
||||
* Timeouts occur when the sink is not connected
|
||||
*/
|
||||
if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
|
||||
printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__);
|
||||
printk(BIOS_SPEW, "dp_aux_ch receive error status 0x%08x\n", status);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Timeouts occur when the device isn't connected, so they're
|
||||
* "normal" -- don't fill the kernel log with these */
|
||||
if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
|
||||
printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__);
|
||||
printk(BIOS_SPEW, "dp_aux_ch timeout status 0x%08x\n", status);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Unload any bytes sent back from the other side */
|
||||
recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
|
||||
DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
|
||||
if (recv_bytes > recv_size)
|
||||
recv_bytes = recv_size;
|
||||
|
||||
for (i = 0; i < recv_bytes; i += 4)
|
||||
unpack_aux(io_i915_read32(ch_data + i),
|
||||
recv + i, recv_bytes - i);
|
||||
|
||||
return recv_bytes;
|
||||
}
|
||||
Loading…
Reference in New Issue