soc/intel/skylake: Add config for cpu base clock frequency

Add config for cpu base clock frequency(Mhz) and replace current
refrence from soc/cpu.h with config option.

Change-Id: Idf8e85f7ae6d965fa987a4f5c4905503ee354d69
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/20016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/skylake/Kconfig

@@ -323,4 +323,8 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
 	int
 	default 2
 
+config CPU_BCLK_MHZ
+	int
+	default 100
+
 endif

src/soc/intel/skylake/acpi.c

@@ -410,7 +410,7 @@ static void generate_p_state_entries(int core, int cores_per_package)
 		/* Max Non-Turbo Ratio */
 		ratio_max = (msr.lo >> 8) & 0xff;
 	}
-	clock_max = ratio_max * CPU_BCLK;
+	clock_max = ratio_max * CONFIG_CPU_BCLK_MHZ;
 
 	/* Calculate CPU TDP in mW */
 	msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
@@ -474,7 +474,7 @@ static void generate_p_state_entries(int core, int cores_per_package)
 
 		/* Calculate power at this ratio */
 		power = calculate_power(power_max, ratio_max, ratio);
-		clock = ratio * CPU_BCLK;
+		clock = ratio * CONFIG_CPU_BCLK_MHZ;
 
 		acpigen_write_PSS_package(
 			clock,			/* MHz */

src/soc/intel/skylake/bootblock/cpu.c

@@ -113,5 +113,5 @@ void set_max_freq(void)
 	wrmsr(MSR_IA32_PERF_CTL, perf_ctl);
 
 	printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n",
-		((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK);
+		((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ);
 }

src/soc/intel/skylake/cpu.c

@@ -320,7 +320,7 @@ static void set_max_ratio(void)
 	wrmsr(IA32_PERF_CTL, perf_ctl);
 
 	printk(BIOS_DEBUG, "cpu: frequency set to %d\n",
-	       ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK);
+	       ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ);
 }
 
 static void set_energy_perf_bias(u8 policy)

src/soc/intel/skylake/include/soc/cpu.h

@@ -34,9 +34,6 @@
 #define CPUID_KABYLAKE_HA0	0x506e8
 #define CPUID_KABYLAKE_HB0	0x906e9
 
-/* CPU bus clock is fixed at 100MHz */
-#define CPU_BCLK		100
-
 /* Latency times in units of 1024ns. */
 #define C_STATE_LATENCY_CONTROL_0_LIMIT	0x4e
 #define C_STATE_LATENCY_CONTROL_1_LIMIT	0x76

src/soc/intel/skylake/tsc_freq.c

@@ -17,7 +17,6 @@
 #include <stdint.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/tsc.h>
-#include <soc/cpu.h>
 #include <soc/msr.h>
 
 unsigned long tsc_freq_mhz(void)
@@ -25,5 +24,5 @@ unsigned long tsc_freq_mhz(void)
 	msr_t platform_info;
 
 	platform_info = rdmsr(MSR_PLATFORM_INFO);
-	return CPU_BCLK * ((platform_info.lo >> 8) & 0xff);
+	return CONFIG_CPU_BCLK_MHZ * ((platform_info.lo >> 8) & 0xff);
 }