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soc/amd/stoneyridge/southbridge: drop ENV_X86 check 

Stoneyridge selects ARCH_X86 unconditionally and all coreboot code will
run on the x86 cores. On Picasso and later, the Chromebooks run verstage
on the PSP which is an ARM V7 core which needs some special handling
cases in the code, but this doesn't apply to Stoneyridge.

TEST=Timeless build results in an identical image for Google/Careena.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I013efd13b56c0191af034a8c4b58e9b26a31c6e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Felix Held 2021-12-07 18:20:38 +01:00
parent c7ab9f410c
commit 105495f37e
1 changed files with 1 additions and 2 deletions
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1
src/soc/amd/stoneyridge/southbridge.c
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@ -230,7 +230,6 @@ void fch_clk_output_48Mhz(u32 osc)
static void sb_init_spi_base(void) static void sb_init_spi_base(void)
{ {
/* Make sure the base address is predictable */ /* Make sure the base address is predictable */
if (ENV_X86)
lpc_set_spibase(SPI_BASE_ADDRESS); lpc_set_spibase(SPI_BASE_ADDRESS);
lpc_enable_spi_rom(SPI_ROM_ENABLE); lpc_enable_spi_rom(SPI_ROM_ENABLE);
} }