AMD: Set the mask of MTRR according to CONFIG_CPU_ADDR_BITS

The high bits of mtrr mask are MBZ (Must be zero). Writing 1 to these
bits will cause exception. So be carefull when spread this change.

The supermicro/h8scm needs more work. Currently it is set as it was.
We need to check if the F10 and F15 have different value.

Change-Id: I2dd8bf07ecee2fe4d1721cec6b21623556e68947
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1661
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

src/cpu/amd/agesa/family12/Kconfig

@@ -23,7 +23,7 @@ config CPU_AMD_AGESA_FAMILY12
 
 config CPU_ADDR_BITS
 	int
-	default 36
+	default 48
 	depends on CPU_AMD_AGESA_FAMILY12
 
 config CPU_SOCKET_TYPE

src/cpu/amd/agesa/family15/Kconfig

@@ -21,6 +21,11 @@ config CPU_AMD_AGESA_FAMILY15
 	bool
 	select PCI_IO_CFG_EXT
 
+config CPU_ADDR_BITS
+	int
+	default 48
+	depends on CPU_AMD_AGESA_FAMILY15
+
 if CPU_AMD_AGESA_FAMILY15
 
 config CPU_AMD_SOCKET_G34

src/cpu/amd/agesa/family15tn/Kconfig

@@ -23,7 +23,7 @@ config CPU_AMD_AGESA_FAMILY15_TN
 
 config CPU_ADDR_BITS
 	int
-	default 36
+	default 48
 	depends on CPU_AMD_AGESA_FAMILY15_TN
 
 config CPU_SOCKET_TYPE

src/mainboard/amd/dinar/agesawrapper.c

@@ -270,7 +270,7 @@ agesawrapper_amdinitmmio (
 	/* Set ROM cache onto WP to decrease post time */
 	MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5;
 	LibAmdMsrWrite (0x20E, &MsrReg, &StdHeader);
-	MsrReg = (0x1000000000000ull - CONFIG_ROM_SIZE) | 0x800;
+	MsrReg = ((1UL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800;
 	LibAmdMsrWrite (0x20F, &MsrReg, &StdHeader);
 
 	Status = AGESA_SUCCESS;

src/mainboard/amd/parmer/agesawrapper.c

@@ -166,7 +166,7 @@ agesawrapper_amdinitmmio (
 	/* Set ROM cache onto WP to decrease post time */
 	MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull;
 	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
-	MsrReg = (0x1000000000000ull - CONFIG_ROM_SIZE) | 0x800ull;
+	MsrReg = ((1UL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull;
 	LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
 
 	Status = AGESA_SUCCESS;

src/mainboard/amd/thatcher/agesawrapper.c

@@ -166,7 +166,7 @@ agesawrapper_amdinitmmio (
 	/* Set ROM cache onto WP to decrease post time */
 	MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull;
 	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
-	MsrReg = (0x1000000000000ull - CONFIG_ROM_SIZE) | 0x800ull;
+	MsrReg = ((1UL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull;
 	LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
 
 	Status = AGESA_SUCCESS;

src/mainboard/amd/torpedo/agesawrapper.c

@@ -281,7 +281,7 @@ agesawrapper_amdinitmmio (
   /* Set ROM cache onto WP to decrease post time */
   MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull;
   LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
-  MsrReg = (0x1000000000000ull - CONFIG_ROM_SIZE) | 0x800ull;
+  MsrReg = ((1UL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull;
   LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
 
   /* Clear all pending SMI. On S3 clear power button enable so it wll not generate an SMI */

src/mainboard/supermicro/h8qgi/agesawrapper.c

@@ -194,7 +194,7 @@ UINT32 agesawrapper_amdinitmmio(VOID)
 	/* Set ROM cache onto WP to decrease post time */
 	MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5;
 	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
-	MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800;
+	MsrReg = ((1UL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800;
 	LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
 
 	Status = AGESA_SUCCESS;

src/mainboard/supermicro/h8scm/Kconfig

@@ -59,6 +59,10 @@ config MAX_PHYSICAL_CPUS
 	int
 	default 16
 
+config CPU_ADDR_BITS
+	int
+	default 36  # TODO: Set it conservatively to match both fam10 & 15
+
 config HW_MEM_HOLE_SIZE_AUTO_INC
 	bool
 	default n

src/mainboard/supermicro/h8scm/agesawrapper.c

@@ -194,7 +194,7 @@ UINT32 agesawrapper_amdinitmmio(VOID)
 	/* Set ROM cache onto WP to decrease post time */
 	MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5;
 	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
-	MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800;
+	MsrReg = ((1UL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800;
 	LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
 
 	Status = AGESA_SUCCESS;

src/mainboard/tyan/s8226/agesawrapper.c

@@ -204,7 +204,7 @@ agesawrapper_amdinitmmio (
 	/* Set ROM cache onto WP to decrease post time */
 	MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull;
 	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
-	MsrReg = (0x1000000000000ull - CONFIG_ROM_SIZE) | 0x800ull;
+	MsrReg = ((1UL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull;
 	LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
 
 	Status = AGESA_SUCCESS;