mb/google/volteer: fix error in generic SPD
The SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex SPD contained an incorrect SDRAM Max Cycle Time (0 instead of 0x0f). After fixing that error, I noticed that two generic SPDs could be collapsed into one, so I removed one of the duplicate generic SPDs (SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_16Row_DDP_4267.spd.hex), and changed Makefile to collapse volteer's DRAM ID 2 into ID 0. BUG=b:156126658, b:156058720 TEST=Flash and boot a ripto to kernel. Also verified that ripto can boot successfully to the kernel at 4267 MT/sec with FSP built in debug mode with RMT enabled. Change-Id: Ib52bf674ebf91854d3d078015aa640aa7ee98a6f Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41345 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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23 11 11 0E 15 21 95 08 00 00 00 00 02 01 00 00
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23 11 11 0E 15 21 95 08 00 00 00 00 02 01 00 00
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48 00 04 00 92 55 00 00 8C 00 90 A8 90 C0 08 60
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48 00 04 0F 92 55 00 00 8C 00 90 A8 90 C0 08 60
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04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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23 11 11 0E 15 21 95 08 00 00 00 00 02 01 00 00
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23 11 11 0E 15 21 95 08 00 00 00 00 02 01 00 00
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48 00 04 00 92 55 00 00 8C 00 90 A8 90 C0 08 60
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48 00 04 0F 92 55 00 00 8C 00 90 A8 90 C0 08 60
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04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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##
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##
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## Memory Options # DRAM ID # Part Num
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## Memory Options # DRAM ID # Part Num
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SPD_SOURCES = SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267 # 0b0000 # K4U6E3S4AA-MGCL
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SPD_SOURCES = SPD_LPDDR4X_200b_1R_16Gb_DDP_4267 # 0b0000 # K4U6E3S4AA-MGCL
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# H9HCNNNBKMMLXR-NEE
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SPD_SOURCES += SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267 # 0b0001 # K4UBE3D4AA-MGCL
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SPD_SOURCES += SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267 # 0b0001 # K4UBE3D4AA-MGCL
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SPD_SOURCES += SPD_LPDDR4X_200b_1R_16Gb_16Row_DDP_4267 # 0b0010 # H9HCNNNBKMMLXR-NEE
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SPD_SOURCES += SPD_LPDDR4X_200b_2R_32Gb_QDP_4267 # 0b0010 # MT53E1G32D2NP-046 WT:A
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SPD_SOURCES += SPD_LPDDR4X_200b_2R_64Gb_ODP_4267 # 0b0011 # H9HCNNNFAMMLXR-NEE
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SPD_SOURCES += SPD_LPDDR4X_200b_2R_64Gb_ODP_4267 # 0b0011 # H9HCNNNFAMMLXR-NEE
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SPD_SOURCES += SPD_LPDDR4X_200b_2R_32Gb_QDP_4267 # 0b0100 # MT53E1G32D2NP-046 WT:A
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23 11 11 0E 15 21 95 08 00 00 00 00 02 01 00 00
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23 11 11 0E 15 21 95 08 00 00 00 00 02 01 00 00
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48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60
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48 00 04 0F 92 55 00 00 8C 00 90 A8 90 C0 08 60
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23 11 11 0E 15 21 95 08 00 00 00 00 02 01 00 00
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48 00 04 00 92 55 00 00 8C 00 90 A8 90 C0 08 60
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04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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