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mb/asrock/g41c-gs: Add IO decode range for SIO HWMON 

Change-Id: Ic02c3a6265f11c1571369bc04371d28b6f989736
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21464
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2017-09-09 12:06:16 +02:00
parent ffdd33c312
commit 106a3e8c7a
1 changed files with 1 additions and 0 deletions
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src/mainboard/asrock/g41c-gs/romstage.c
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@ -75,6 +75,7 @@ static void ich7_enable_lpc(void)
/* Decode range */ /* Decode range */
pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN
| KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN);
pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0291);
} }
void mainboard_romstage_entry(unsigned long bist) void mainboard_romstage_entry(unsigned long bist)