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mb/google/fizz: Set SATA GPIOs in bootblock 

Previously, we were seeing device boot into the recovery screen with
error code 0x5a.  This was root caused to the SATA GPIOs (specifically
DEVSLP) not being initialized early enough, causing the SATA 1 link
detection to time out and the device to reboot into recovery with
0x5a instead of booting into the OS as usual.

BUG=b:69715162
BRANCH=None
TEST=after flashing BIOS, set gbb flags to 0, then type reboot from
     the OS.

Change-Id: I53913d5b7adaeb43edd0ef2d24a7cad92052d68a
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Shelley Chen 2018-02-07 17:29:19 -08:00 committed by Martin Roth
parent f0b3a5fe4f
commit 106a9fe882
1 changed files with 6 additions and 3 deletions
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9
src/mainboard/google/fizz/gpio.h
View File

@ -179,9 +179,9 @@ static const struct pad_config gpio_table[] = {
/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, 20K_PU, DEEP,
NF1), /* DB_PCIE_SATA#_DET */
/* CPU_GP0 */ PAD_CFG_NC(GPP_E3),
/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4),
/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_DB */
/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), /* TP328 */
/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), /* TP103 */
/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */
/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), /* DEVSLP2_DB */
/* CPU_GP1 */ PAD_CFG_NC(GPP_E7),
/* SATALED# */ PAD_CFG_NC(GPP_E8), /* TP314 */
/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB-C */
@ -276,6 +276,9 @@ static const struct pad_config early_gpio_table[] = {
/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE,
DEEP), /* SCREW_SPI_WP_STATUS */
/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP,
NF1), /* MB_PCIE_SATA#_DET */
/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */
};
#endif