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cpu/intel: Remove models 69x and 6dx 

These came for the Socket 479 which is not supported anymore.

Change-Id: I0cf7ece028baa6750b79f54d615e93e452aff2e1
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31644
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nico Huber 2019-02-27 14:29:24 +01:00 committed by Patrick Georgi
parent ec6d07a330
commit 1083a4d232
7 changed files with 0 additions and 121 deletions
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2
src/cpu/intel/Kconfig
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@ -3,9 +3,7 @@ source src/cpu/intel/model_6xx/Kconfig
source src/cpu/intel/model_65x/Kconfig
source src/cpu/intel/model_67x/Kconfig
source src/cpu/intel/model_68x/Kconfig
source src/cpu/intel/model_69x/Kconfig
source src/cpu/intel/model_6bx/Kconfig
source src/cpu/intel/model_6dx/Kconfig
source src/cpu/intel/model_6ex/Kconfig
source src/cpu/intel/model_6fx/Kconfig
source src/cpu/intel/model_1067x/Kconfig

8
src/cpu/intel/model_69x/Kconfig
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@ -1,8 +0,0 @@
config CPU_INTEL_MODEL_69X
bool
select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SMP
select SUPPORT_CPU_UCODE_IN_CBFS

3
src/cpu/intel/model_69x/Makefile.inc
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@ -1,3 +0,0 @@
ramstage-y += model_69x_init.c
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_69x/microcode.bin

48
src/cpu/intel/model_69x/model_69x_init.c
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@ -1,48 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/device.h>
#include <cpu/cpu.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/lapic.h>
#include <cpu/intel/microcode.h>
#include <cpu/x86/cache.h>
static void model_69x_init(struct device *dev)
{
/* Turn on caching if we haven't already */
x86_enable_cache();
x86_setup_mtrrs();
x86_mtrr_check();
/* Update the microcode */
intel_update_microcode_from_cbfs();
/* Enable the local CPU APICs */
setup_lapic();
};
static struct device_operations cpu_dev_ops = {
.init = model_69x_init,
};
static const struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_INTEL, 0x0690 }, /* Pentium M */
{ X86_VENDOR_INTEL, 0x0695 },
{ 0, 0 },
};
static const struct cpu_driver driver __cpu_driver = {
.ops = &cpu_dev_ops,
.id_table = cpu_table,
};

8
src/cpu/intel/model_6dx/Kconfig
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@ -1,8 +0,0 @@
config CPU_INTEL_MODEL_6DX
bool
select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SMP
select SUPPORT_CPU_UCODE_IN_CBFS

3
src/cpu/intel/model_6dx/Makefile.inc
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@ -1,3 +0,0 @@
ramstage-y += model_6dx_init.c
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6dx/microcode.bin

49
src/cpu/intel/model_6dx/model_6dx_init.c
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@ -1,49 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/device.h>
#include <cpu/cpu.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/lapic.h>
#include <cpu/intel/microcode.h>
#include <cpu/x86/cache.h>
static void model_6dx_init(struct device *dev)
{
/* Turn on caching if we haven't already */
x86_enable_cache();
x86_setup_mtrrs();
x86_mtrr_check();
/* Update the microcode */
intel_update_microcode_from_cbfs();
/* Enable the local CPU APICs */
setup_lapic();
};
static struct device_operations cpu_dev_ops = {
.init = model_6dx_init,
};
static const struct cpu_device_id cpu_table[] = {
/* Pentium M on 90nm with 2MiB of L2 cache */
{ X86_VENDOR_INTEL, 0x06D0 },
{ X86_VENDOR_INTEL, 0x06D6 },
{ 0, 0 },
};
static const struct cpu_driver driver __cpu_driver = {
.ops = &cpu_dev_ops,
.id_table = cpu_table,
};