preliminary GX DRAM initization. It is not working yet.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2181 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Li-Ta Lo
parent
02bb7892fe
commit
108dd2c01e
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@ -14,7 +14,6 @@
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#define NORTHBRIDGE_FILE "northbridge.c"
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/*
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*/
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static void optimize_xbus(device_t dev)
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{
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/* Optimise X-Bus performance */
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@ -119,7 +118,7 @@ static void pci_domain_set_resources(device_t dev)
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{
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device_t mc_dev;
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uint32_t pci_tolm;
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#if 0
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pci_tolm = find_pci_tolm(&dev->link[0]);
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mc_dev = dev->link[0].children;
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if (mc_dev) {
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@ -162,6 +161,7 @@ static void pci_domain_set_resources(device_t dev)
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ram_resource(dev, idx++, 0, tolmk);
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}
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assign_resources(&dev->link[0]);
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#endif
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}
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static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
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@ -1,357 +1,111 @@
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#include <cpu/amd/gx2def.h>
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/*
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This software and ancillary information (herein called SOFTWARE )
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called LinuxBIOS is made available under the terms described
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here. The SOFTWARE has been approved for release with associated
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LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has
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been authored by an employee or employees of the University of
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California, operator of the Los Alamos National Laboratory under
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Contract No. W-7405-ENG-36 with the U.S. Department of Energy. The
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U.S. Government has rights to use, reproduce, and distribute this
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SOFTWARE. The public may copy, distribute, prepare derivative works
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and publicly display this SOFTWARE without charge, provided that this
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Notice and any statement of authorship are reproduced on all copies.
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Neither the Government nor the University makes any warranty, express
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or implied, or assumes any liability or responsibility for the use of
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this SOFTWARE. If SOFTWARE is modified to produce derivative works,
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such modified SOFTWARE should be clearly marked, so as not to confuse
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it with the version available from LANL.
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*/
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/* Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL
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* rminnich@lanl.gov
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*/
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/* SDRAM initialization for GX1 - translated from Christer Weinigel's
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assembler version into C.
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Hamish Guthrie 10/4/2005 hamish@prodigi.ch
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*/
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/* just converted to GX2 by ron minnich -- this is probably mostly wrong
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* I am just putting in a placeholder to start building gx2 support
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*/
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#define NUM_REFRESH 8
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#define TEST_DATA1 0x05A5A5A5A
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#define TEST_DATA2 0x0DEADBEEF
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void setGX2Mem(unsigned int addr, unsigned int data)
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static void sdram_set_registers(const struct mem_controller *ctrl)
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{
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writel(data, (volatile void *)addr);
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}
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unsigned int getGX2Mem(unsigned int addr)
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static void sdram_set_spd_registers(const struct mem_controller *ctrl)
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{
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return (unsigned int)readl((const volatile void *)addr);
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}
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void do_refresh(void)
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{
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unsigned int tval, i;
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outb(0x71, 0x80);
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tval = getGX2Mem(GX_BASE + MC_MEM_CNTRL1);
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tval |= RFSHTST;
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for(i=0; i>NUM_REFRESH; i++)
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setGX2Mem(GX_BASE + MC_MEM_CNTRL1, tval);
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outb(0x72, 0x80);
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}
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void enable_dimm(void)
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{
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unsigned int tval, i;
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outb(0x73, 0x80);
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/* start SDCLCK's */
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tval = getGX2Mem(GX_BASE + MC_MEM_CNTRL1);
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tval &= ~SDCLKSTRT;
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setGX2Mem(GX_BASE + MC_MEM_CNTRL1, tval);
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tval |= SDCLKSTRT;
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setGX2Mem(GX_BASE + MC_MEM_CNTRL1, tval);
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/* Unmask SDCLK's */
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tval = getGX2Mem(GX_BASE + MC_MEM_CNTRL2);
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tval &= ~(SDCLK_MASK | SDCLKOUT_MASK);
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setGX2Mem(GX_BASE + MC_MEM_CNTRL2, tval);
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tval = getGX2Mem(GX_BASE + MC_MEM_CNTRL2);
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/* Wait for clocks to unmask */
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for(i=0; i<5000; i++)
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outb(0, 0xed);
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/* Refresh memory */
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tval = getGX2Mem(GX_BASE + MC_MEM_CNTRL1);
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tval |= RFSHTST;
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for(i=0; i<NUM_REFRESH; i++)
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setGX2Mem(GX_BASE + MC_MEM_CNTRL1, tval);
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tval &= ~RFSHTST;
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/* Start the SDCLK's */
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tval &= ~PROGRAM_SDRAM;
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setGX2Mem(GX_BASE + MC_MEM_CNTRL1, tval);
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tval |= PROGRAM_SDRAM | 0x00002000; /* Set refresh timing */
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setGX2Mem(GX_BASE + MC_MEM_CNTRL1, tval);
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tval &= ~PROGRAM_SDRAM;
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setGX2Mem(GX_BASE + MC_MEM_CNTRL1, tval);
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/* Refresh memory again */
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tval = getGX2Mem(GX_BASE + MC_MEM_CNTRL1);
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tval |= RFSHTST;
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for(i=0; i>NUM_REFRESH; i++)
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setGX2Mem(GX_BASE + MC_MEM_CNTRL1, tval);
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for(i=0; i<2000; i++)
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outb(0, 0xed);
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outb(0x74, 0x80);
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}
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static unsigned int size_dimm(int dimm_shift)
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/* Section 6.1.3, LX processor databooks, BIOS Initialization Sequence
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* Section 4.1.4, GX/CS5535 GeodeROM Porting guide */
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static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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{
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int bank_cfg = 0x700; /* MC_BANK_CFG for 512M */
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unsigned int offset = 0x10000000; /* Offset 256M */
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int failed_flag = 1;
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int i;
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msr_t msr;
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do {
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setGX2Mem(0, TEST_DATA1);
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setGX2Mem(offset, TEST_DATA2);
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setGX2Mem(0x100, 0); /* Clear the bus */
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if (getGX2Mem(0) != TEST_DATA1) {
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setGX2Mem(GX_BASE + MC_BANK_CFG,
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getGX2Mem(GX_BASE + MC_BANK_CFG) & ~(DIMM_SZ << dimm_shift));
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bank_cfg -= 0x100;
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setGX2Mem(GX_BASE + MC_BANK_CFG,
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getGX2Mem(GX_BASE + MC_BANK_CFG) | (bank_cfg << dimm_shift));
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do_refresh();
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offset >>= 1;
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} else {
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failed_flag = 0;
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break;
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}
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} while (bank_cfg >= 0);
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/* 1. Initialize GLMC registers base on SPD values,
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* Hard coded as XpressROM for now */
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print_debug("sdram_enable step 1\r\n");
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msr = rdmsr(0x20000018);
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msr.hi = 0x10076013;
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msr.lo = 0x00004800;
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wrmsr(0x20000018, msr);
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if (failed_flag)
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return (0x0070 << dimm_shift);
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else
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return(getGX2Mem(GX_BASE + MC_BANK_CFG) & (DIMM_SZ << dimm_shift));
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}
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msr = rdmsr(0x20000019);
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msr.hi = 0x18000108;
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msr.lo = 0x286332a3;
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wrmsr(0x20000019, msr);
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static unsigned int module_banks(int dimm_shift)
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{
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int page_size = 0x800; /* Smallest page = 1K * 2 banks */
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int comp_banks;
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/* 2. release from PMode */
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msr = rdmsr(0x20002004);
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msr.lo &= !0x04;
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msr.lo |= 0x01;
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wrmsr(0x20002004, msr);
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/* undocmented bits in GX, in LX there are
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* 8 bits in PM1_UP_DLY */
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msr = rdmsr(0x2000001a);
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//msr.lo |= 0xF000;
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msr.lo = 0x0101;
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wrmsr(0x2000001a, msr);
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print_debug("sdram_enable step 2\r\n");
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#if 0
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print_debug("MC_BANK_CFG = ");
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print_debug_hex32(getGX2Mem(GX_BASE + MC_BANK_CFG));
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print_debug("\r\n");
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#endif
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/* 3. release CKE mask to enable CKE */
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msr = rdmsr(0x2000001d);
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msr.lo &= !(0x03 << 8);
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wrmsr(0x2000201d, msr);
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print_debug("sdram_enable step 3\r\n");
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/* retrieve the page size from the MC register */
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page_size <<= (((getGX2Mem(GX_BASE + MC_BANK_CFG) & (DIMM_PG_SZ << dimm_shift)) >> dimm_shift) >> 4);
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#if 0
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print_debug(" page_size = ");
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print_debug_hex32(page_size);
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print_debug("\r\n");
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#endif
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comp_banks = (((getGX2Mem(GX_BASE + MC_BANK_CFG) & (DIMM_COMP_BNK << dimm_shift)) >> dimm_shift) >> 12);
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page_size <<= comp_banks;
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setGX2Mem(0, TEST_DATA1);
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setGX2Mem(page_size, TEST_DATA2);
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setGX2Mem(0x100, 0); /* Clear the bus */
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if (getGX2Mem(page_size) != TEST_DATA2) {
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setGX2Mem(GX_BASE + MC_BANK_CFG,
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getGX2Mem(GX_BASE + MC_BANK_CFG) & ~(DIMM_MOD_BNK << dimm_shift));
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do_refresh();
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/* 4. set and clear REF_TST 16 times, more shouldn't hurt */
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for (i = 0; i < 19; i++) {
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msr = rdmsr(0x20000018);
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msr.lo |= (0x01 << 3);
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wrmsr(0x20000018, msr);
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msr.lo &= !(0x01 << 3);
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wrmsr(0x20000018, msr);
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}
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#if 0
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print_debug("MC_BANK_CFG = ");
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print_debug_hex32(getGX2Mem(GX_BASE + MC_BANK_CFG));
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print_debug("\r\n");
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#endif
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return(getGX2Mem(GX_BASE + MC_BANK_CFG) & (DIMM_MOD_BNK << dimm_shift));
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}
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static unsigned int component_banks(int dimm_shift)
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{
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int page_size = 0x800; /* Smallest page = 1K * 2 banks */
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#if 0
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print_debug("MC_BANK_CFG = ");
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print_debug_hex32(getGX2Mem(GX_BASE + MC_BANK_CFG));
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print_debug("\r\n");
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#endif
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page_size = page_size << (((getGX2Mem(GX_BASE + MC_BANK_CFG) & (DIMM_PG_SZ << dimm_shift)) >> dimm_shift) >> 4);
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#if 0
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print_debug(" page_size = ");
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print_debug_hex32(page_size);
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print_debug("\r\n");
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#endif
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setGX2Mem(0, TEST_DATA1);
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setGX2Mem(page_size, TEST_DATA2);
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setGX2Mem(0x100, 0); /* Clear the bus */
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if (getGX2Mem(0) != TEST_DATA1) {
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setGX2Mem(GX_BASE + MC_BANK_CFG,
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getGX2Mem(GX_BASE + MC_BANK_CFG) & ~(DIMM_COMP_BNK << dimm_shift));
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do_refresh();
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}
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#if 0
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print_debug("MC_BANK_CFG = ");
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print_debug_hex32(getGX2Mem(GX_BASE + MC_BANK_CFG));
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print_debug("\r\n");
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#endif
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return(getGX2Mem(GX_BASE + MC_BANK_CFG) & (DIMM_COMP_BNK << dimm_shift));
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}
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static unsigned int page_size(int dimm_shift)
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{
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unsigned int page_test_offset = 0x2000;
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unsigned int temp;
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int page_size_config = 0x40;
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unsigned int probe_config;
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do {
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setGX2Mem(0, TEST_DATA1);
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setGX2Mem(page_test_offset, TEST_DATA2);
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setGX2Mem(0x100, 0);
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temp = getGX2Mem(0);
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setGX2Mem(0, 0);
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if(temp == TEST_DATA1) {
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#if 0
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print_debug(" Page size Config = ");
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print_debug_hex32(page_size_config << dimm_shift);
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print_debug("\r\n");
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#endif
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return(page_size_config << dimm_shift);
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}
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temp = ~(DIMM_PG_SZ << dimm_shift);
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probe_config = getGX2Mem(GX_BASE + MC_BANK_CFG);
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probe_config &= temp;
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page_size_config -= 0x10;
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page_size_config <<= dimm_shift;
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probe_config |= page_size_config;
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page_size_config >>= dimm_shift;
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page_test_offset >>= 1;
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setGX2Mem(GX_BASE + MC_BANK_CFG, probe_config);
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do_refresh();
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} while (page_size_config >= 0);
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return 0x70;
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}
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static int dimm_detect(int dimm_shift)
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{
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unsigned int test;
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print_debug("Probing for DIMM");
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print_debug_char((dimm_shift >> 4) + 0x30);
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print_debug("\r\n");
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setGX2Mem(0, TEST_DATA1);
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setGX2Mem(0x100, 0);
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test = getGX2Mem(0);
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setGX2Mem(0, 0);
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if (test != TEST_DATA1)
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return 0;
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print_debug(" Found DIMM");
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print_debug_char((dimm_shift >> 4) + 0x30);
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print_debug("\r\n");
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return 1;
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}
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static int size_memory(int dimm_shift, unsigned int mem_config)
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{
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if (!dimm_detect(dimm_shift))
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return (mem_config);
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mem_config &= (~(DIMM_PG_SZ << dimm_shift));
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mem_config |= (page_size(dimm_shift));
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print_debug(" Page Size: ");
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print_debug_hex32(0x400 << ((mem_config & (DIMM_PG_SZ << dimm_shift)) >> (dimm_shift + 4)));
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print_debug("\r\n");
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/* Now do component banks detection */
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mem_config &= (~(DIMM_COMP_BNK << dimm_shift));
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mem_config |= (component_banks(dimm_shift));
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print_debug(" Component Banks: ");
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print_debug_char((((mem_config & (DIMM_COMP_BNK << dimm_shift)) >> (dimm_shift + 12)) ? 4 : 2) + 0x30);
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print_debug("\r\n");
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/* Now do module banks */
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mem_config &= (~(DIMM_MOD_BNK << dimm_shift));
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mem_config |= (module_banks(dimm_shift));
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print_debug(" Module Banks: ");
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print_debug_char((((mem_config & (DIMM_MOD_BNK << dimm_shift)) >> (dimm_shift + 14)) ? 2 : 1) + 0x30);
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print_debug("\r\n");
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mem_config &= (~(DIMM_SZ << dimm_shift));
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mem_config |= (size_dimm(dimm_shift));
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print_debug(" DIMM size: ");
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print_debug_hex32(1 <<
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((mem_config & (DIMM_SZ << dimm_shift)) >> (dimm_shift + 8)) + 22);
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print_debug("\r\n");
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return (mem_config);
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}
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static void sdram_init(void)
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{
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unsigned int mem_config = 0x00700070;
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print_debug("Setting up default parameters for memory\r\n");
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outb(0x70, 0x80);
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setGX2Mem(GX_BASE + MC_MEM_CNTRL2, 0x000007d8); /* Disable all CLKS, Shift = 3 */
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setGX2Mem(GX_BASE + MC_MEM_CNTRL1, 0x92140000); /* MD_DS=2, MA_DS=2, CNTL_DS=2 SDCLKRATE=4 */
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setGX2Mem(GX_BASE + MC_BANK_CFG, 0x00700070); /* No DIMMS installed */
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setGX2Mem(GX_BASE + MC_SYNC_TIM1, 0x3a733225); /* LTMODE=3, RC=10, RAS=7, RP=3, RCD=3, RRD=2, DPL=2 */
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setGX2Mem(GX_BASE + MC_BANK_CFG, 0x57405740); /* Largest DIMM size
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0x4000 -- 2 module banks
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0x1000 -- 4 component banks
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0x0700 -- DIMM size 512MB
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0x0040 -- Page Size 16kB */
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enable_dimm();
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print_debug("Sizing memory\r\n");
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setGX2Mem(GX_BASE + MC_BANK_CFG, 0x00705740);
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do_refresh();
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mem_config = size_memory(0, mem_config);
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setGX2Mem(GX_BASE + MC_BANK_CFG, 0x57400070);
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do_refresh();
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mem_config = size_memory(16, mem_config);
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print_debug("MC_BANK_CFG = ");
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print_debug_hex32(mem_config);
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print_debug("\r\n");
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setGX2Mem(GX_BASE + MC_BANK_CFG, mem_config);
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enable_dimm();
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outb(0x7e, 0x80);
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print_debug("sdram_enable step 4\r\n");
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/* 5. set refresh interval */
|
||||
msr = rdmsr(0x20000018);
|
||||
msr.lo |= (0x48 << 8);
|
||||
wrmsr(0x20000018, msr);
|
||||
|
||||
/* set refresh staggering to 4 SDRAM clocks */
|
||||
msr = rdmsr(0x20000018);
|
||||
msr.lo &= !(0x03 << 6);
|
||||
wrmsr(0x20000018, msr);
|
||||
|
||||
|
||||
/* 6. enable RLL, load Extended Mode Register by set and clear PROG_DRAM */
|
||||
msr = rdmsr(0x20000018);
|
||||
msr.lo |= ((0x01 << 28) | 0x01);
|
||||
wrmsr(0x20000018, msr);
|
||||
msr.lo &= !((0x01 << 28) | 0x01);
|
||||
wrmsr(0x20000018, msr);
|
||||
print_debug("sdram_enable step 7\r\n");
|
||||
|
||||
/* 7. Reset DLL, Bit 27 is undocumented in GX datasheet,
|
||||
* it is documented in LX datasheet */
|
||||
/* load Mode Register by set and clear PROG_DRAM */
|
||||
msr = rdmsr(0x20000018);
|
||||
msr.lo |= ((0x01 << 27) | 0x01);
|
||||
wrmsr(0x20000018, msr);
|
||||
msr.lo &= !((0x01 << 27) | 0x01);
|
||||
wrmsr(0x20000018, msr);
|
||||
print_debug("sdram_enable step 9\r\n");
|
||||
|
||||
|
||||
/* 8. load Mode Register by set and clear PROG_DRAM */
|
||||
msr = rdmsr(0x20000018);
|
||||
msr.lo |= 0x01;
|
||||
wrmsr(0x20000018, msr);
|
||||
msr.lo &= !0x01;
|
||||
wrmsr(0x20000018, msr);
|
||||
print_debug("sdram_enable step 10\r\n");
|
||||
|
||||
/* wait 200 SDCLKs */
|
||||
for (i = 0; i < 200; i++)
|
||||
outb(0xaa, 0x80);
|
||||
|
||||
/* load RDSYNC */
|
||||
msr = rdmsr(0x2000001a);
|
||||
msr.hi = 0x000ff310;
|
||||
wrmsr(0x20000018, msr);
|
||||
print_debug("sdram_enable step 10\r\n");
|
||||
|
||||
/* DRAM working now?? */
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,11 +1,10 @@
|
|||
#ifndef RAMINIT_H
|
||||
#define RAMINIT_H
|
||||
|
||||
#define DIMM_SOCKETS 4
|
||||
#define DIMM_SOCKETS 2
|
||||
|
||||
struct mem_controller {
|
||||
device_t d0;
|
||||
uint16_t channel0[DIMM_SOCKETS];
|
||||
uint16_t channel0[DIMM_SOCKETS];
|
||||
};
|
||||
|
||||
|
||||
#endif /* RAMINIT_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue