intel/xeon_sp: Add ACPI to control GPIO
This has been tested on the OCP Delta Lake platform. Change-Id: I07c882077eb3c035faae81641bc860e69db224b4 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao
This commit is contained in:
Maxim Polyakov
Patrick Georgi
parent
3865a33231
commit
1090b16b98
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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#include <soc/gpio.h>
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#include <soc/pcr_ids.h>
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#include <soc/irq.h>
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#include <soc/intel/common/block/acpi/acpi/gpio_op.asl>
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#include <soc/intel/common/acpi/pcr.asl>
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Device (GPIO)
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{
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Name (_HID, "INT3536")
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Name (_UID, 0)
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Name (_DDN, "GPIO Controller")
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Name (RBUF, ResourceTemplate()
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{
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Memory32Fixed (ReadWrite, 0, 0, COM0)
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Memory32Fixed (ReadWrite, 0, 0, COM1)
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Memory32Fixed (ReadWrite, 0, 0, COM2)
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Memory32Fixed (ReadWrite, 0, 0, COM3)
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Memory32Fixed (ReadWrite, 0, 0, COM4)
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Memory32Fixed (ReadWrite, 0, 0, COM5)
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Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) { PCH_IRQ14 }
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})
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/* Current Resource Settings */
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Method (_CRS, 0, NotSerialized)
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{
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/* GPIO Community 0 */
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CreateDWordField (^RBUF, ^COM0._BAS, BAS0)
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CreateDWordField (^RBUF, ^COM0._LEN, LEN0)
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BAS0 = ^^PCRB (PID_GPIOCOM0)
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LEN0 = GPIO_BASE_SIZE
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/* GPIO Community 1 */
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CreateDWordField (^RBUF, ^COM1._BAS, BAS1)
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CreateDWordField (^RBUF, ^COM1._LEN, LEN1)
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BAS1 = ^^PCRB (PID_GPIOCOM1)
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LEN1 = GPIO_BASE_SIZE
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/* GPIO Community 2 */
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CreateDWordField (^RBUF, ^COM2._BAS, BAS2)
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CreateDWordField (^RBUF, ^COM2._LEN, LEN2)
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BAS2 = ^^PCRB (PID_GPIOCOM2)
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LEN2 = GPIO_BASE_SIZE
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/* GPIO Community 3 */
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CreateDWordField (^RBUF, ^COM3._BAS, BAS3)
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CreateDWordField (^RBUF, ^COM3._LEN, LEN3)
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BAS3 = ^^PCRB (PID_GPIOCOM3)
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LEN3 = GPIO_BASE_SIZE
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/* GPIO Community 4 */
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CreateDWordField (^RBUF, ^COM4._BAS, BAS4)
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CreateDWordField (^RBUF, ^COM4._LEN, LEN4)
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BAS4 = ^^PCRB (PID_GPIOCOM4)
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LEN4 = GPIO_BASE_SIZE
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/* GPIO Community 5 */
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CreateDWordField (^RBUF, ^COM5._BAS, BAS5)
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CreateDWordField (^RBUF, ^COM5._LEN, LEN5)
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BAS5 = ^^PCRB (PID_GPIOCOM5)
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LEN5 = GPIO_BASE_SIZE
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Return (RBUF)
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}
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/* Return status of power resource */
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Method (_STA, 0, NotSerialized)
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{
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Return (0xF)
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}
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}
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/*
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* Get GPIO DW0 Address
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* Arg0 - GPIO Number
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*/
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Method (GADD, 1, NotSerialized)
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{
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/* GPIO Community 0 */
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if ((Arg0 >= GPP_A0) && (Arg0 <= GPP_F23))
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{
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Local0 = PID_GPIOCOM0
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Local1 = Arg0 - GPP_A0
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}
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/* GPIO Community 1 */
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if ((Arg0 >= GPP_C0) && (Arg0 <= GPP_E12))
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{
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Local0 = PID_GPIOCOM1
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Local1 = Arg0 - GPP_C0
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}
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/* GPIO Community 2 */
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if ((Arg0 >= GPD0) && (Arg0 <= GPD11))
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{
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Local0 = PID_GPIOCOM2
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Local1 = Arg0 - GPD0
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}
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/* GPIO Community 3 */
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if ((Arg0 >= GPP_I0) && (Arg0 <= GPP_I10))
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{
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Local0 = PID_GPIOCOM3
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Local1 = Arg0 - GPP_I0
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}
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/* GPIO Community 4 */
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if ((Arg0 >= GPP_J0) && (Arg0 <= GPP_K10))
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{
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Local0 = PID_GPIOCOM4
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Local1 = Arg0 - GPP_J0
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}
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/* GPIO Community 5 */
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if ((Arg0 >= GPP_G0) && (Arg0 <= GPP_L19))
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{
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Local0 = PID_GPIOCOM5
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Local1 = Arg0 - GPP_G0
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}
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Local2 = PCRB (Local0)
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Local2 += PAD_CFG_BASE
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Return (Local2 + (Local1 * 8))
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}
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/*
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* Return PCR Port ID of GPIO Communities
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*
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* Arg0: GPIO Community (0-5)
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*/
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Method (GPID, 1, Serialized)
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{
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Switch (ToInteger (Arg0))
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{
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Case (COMM_0)
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{
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Local0 = PID_GPIOCOM0
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}
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Case (COMM_1)
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{
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Local0 = PID_GPIOCOM1
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}
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Case (COMM_2)
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{
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Local0 = PID_GPIOCOM2
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}
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Case (COMM_3)
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{
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Local0 = PID_GPIOCOM3
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}
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Case (COMM_4)
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{
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Local0 = PID_GPIOCOM4
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}
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Case (COMM_5)
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{
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Local0 = PID_GPIOCOM5
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}
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Default
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{
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Return (0)
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}
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}
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Return (Local0)
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}
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@ -2,5 +2,8 @@
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/* This file should be included in the proper platform ACPI \_SB PCI scope */
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/* GPIO */
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#include <soc/intel/xeon_sp/acpi/gpio.asl>
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/* LPC 0:1f.0 */
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#include <soc/intel/common/block/acpi/acpi/lpc.asl>
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@ -33,5 +33,6 @@
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#define PCH_PWRM_BASE_SIZE 0x10000
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#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS
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#define GPIO_BASE_SIZE 0x10000
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#endif /* _SOC_IOMAP_H_ */
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@ -5,5 +5,6 @@
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#define PCH_IRQ10 10
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#define PCH_IRQ11 11
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#define PCH_IRQ14 14
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#endif /* _SOC_IRQ_H_ */
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