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soc/intel/meteorlake: Fill ucode loading UPD if USE_FSP_MP_INIT enable 

This patch calls into a helper function to fill `2nd microcode loading
FSP UPD` if FSP is running CPU feature programming.

This patch is backported from
commit fad1cb062e (soc/intel/alderlake:
Fill ucode loading UPD if USE_FSP_MP_INIT enable).

Change-Id: Id8c8bfd844b3213cc260df20c359b0b1437e3e28
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70599
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
This commit is contained in:
Subrata Banik 2022-12-09 13:31:47 +05:30
parent b25aeb5937
commit 10929ef008
1 changed files with 19 additions and 6 deletions
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21
src/soc/intel/meteorlake/fsp_params.c
View File

@ -4,6 +4,7 @@
#include <cbfs.h> #include <cbfs.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/intel/cpu_ids.h> #include <cpu/intel/cpu_ids.h>
#include <cpu/intel/microcode.h>
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <fsp/api.h> #include <fsp/api.h>
@ -119,22 +120,34 @@ static void fill_fsps_lpss_params(FSP_S_CONFIG *s_cfg,
} }
} }
static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg, static void fill_fsps_microcode_params(FSP_S_CONFIG *s_cfg,
const struct soc_intel_meteorlake_config *config) const struct soc_intel_meteorlake_config *config)
{ {
const struct microcode *microcode_file; const struct microcode *microcode_file;
size_t microcode_len; size_t microcode_len;
/* Locate microcode and pass to FSP-S for 2nd microcode loading */ /* Locate microcode and pass to FSP-S for 2nd microcode loading */
microcode_file = cbfs_map("cpu_microcode_blob.bin", &microcode_len); microcode_file = intel_microcode_find();
if ((microcode_file) && (microcode_len != 0)) { if (microcode_file != NULL) {
microcode_len = get_microcode_size(microcode_file);
if (microcode_len != 0) {
/* Update CPU Microcode patch base address/size */ /* Update CPU Microcode patch base address/size */
s_cfg->MicrocodeRegionBase = (uint32_t)microcode_file; s_cfg->MicrocodeRegionBase = (uint32_t)(uintptr_t)microcode_file;
s_cfg->MicrocodeRegionSize = (uint32_t)microcode_len; s_cfg->MicrocodeRegionSize = (uint32_t)microcode_len;
} }
}
}
static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg,
const struct soc_intel_meteorlake_config *config)
{
if (CONFIG(MTL_USE_FSP_MP_INIT)) { if (CONFIG(MTL_USE_FSP_MP_INIT)) {
/*
* Fill `2nd microcode loading FSP UPD` if FSP is running CPU feature
* programming.
*/
fill_fsps_microcode_params(s_cfg, config);
/* /*
* Use FSP running MP PPI services to perform CPU feature programming * Use FSP running MP PPI services to perform CPU feature programming
* if Kconfig is enabled * if Kconfig is enabled