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AGESA/binaryPI: Drop invalid AMD_AGESA_BOLTON 

I refused bolton under agesa/ once it turned out to be
blobbed. We have AMD_PI_BOLTON.

Change-Id: Ic3cb9ada2d4f14b49f6ad54c58e6b950a1732b70
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Kyösti Mälkki 2019-01-10 10:00:38 +02:00
parent 76f5b225e2
commit 109a58a852
7 changed files with 9 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/northbridge/amd/agesa/state_machine.h
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@ -98,7 +98,6 @@ void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save);
#define HAS_AGESA_FCH_OEM_CALLOUT \ #define HAS_AGESA_FCH_OEM_CALLOUT \
IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) || \ IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) || \
IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) || \ IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) || \
IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || \
IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) || \ IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) || \
IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) || \ IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) || \
IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN)

1
src/southbridge/amd/agesa/Makefile.inc
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@ -13,6 +13,5 @@
# GNU General Public License for more details. # GNU General Public License for more details.
# #
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) += hudson
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += hudson subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += hudson
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += hudson subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += hudson

10
src/southbridge/amd/agesa/hudson/Kconfig
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@ -13,16 +13,13 @@
## GNU General Public License for more details. ## GNU General Public License for more details.
## ##
config SOUTHBRIDGE_AMD_AGESA_BOLTON
bool
config SOUTHBRIDGE_AMD_AGESA_HUDSON config SOUTHBRIDGE_AMD_AGESA_HUDSON
bool bool
config SOUTHBRIDGE_AMD_AGESA_YANGTZE config SOUTHBRIDGE_AMD_AGESA_YANGTZE
bool bool
if SOUTHBRIDGE_AMD_AGESA_BOLTON || SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE if SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE
config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy
def_bool y def_bool y
@ -76,21 +73,18 @@ config HUDSON_GEC_FWM
config HUDSON_XHCI_FWM_FILE config HUDSON_XHCI_FWM_FILE
string "XHCI firmware path and filename" string "XHCI firmware path and filename"
default "3rdparty/blobs/southbridge/amd/bolton/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_BOLTON
default "3rdparty/blobs/southbridge/amd/hudson/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON default "3rdparty/blobs/southbridge/amd/hudson/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON
default "3rdparty/blobs/southbridge/amd/yangtze/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE default "3rdparty/blobs/southbridge/amd/yangtze/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE
depends on HUDSON_XHCI_FWM depends on HUDSON_XHCI_FWM
config HUDSON_IMC_FWM_FILE config HUDSON_IMC_FWM_FILE
string "IMC firmware path and filename" string "IMC firmware path and filename"
default "3rdparty/blobs/southbridge/amd/bolton/imc.bin" if SOUTHBRIDGE_AMD_AGESA_BOLTON
default "3rdparty/blobs/southbridge/amd/hudson/imc.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON default "3rdparty/blobs/southbridge/amd/hudson/imc.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON
default "3rdparty/blobs/southbridge/amd/yangtze/imc.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE default "3rdparty/blobs/southbridge/amd/yangtze/imc.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE
depends on HUDSON_IMC_FWM depends on HUDSON_IMC_FWM
config HUDSON_GEC_FWM_FILE config HUDSON_GEC_FWM_FILE
string "GEC firmware path and filename" string "GEC firmware path and filename"
default "3rdparty/blobs/southbridge/amd/bolton/gec.bin" if SOUTHBRIDGE_AMD_AGESA_BOLTON
default "3rdparty/blobs/southbridge/amd/hudson/gec.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON default "3rdparty/blobs/southbridge/amd/hudson/gec.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON
default "3rdparty/blobs/southbridge/amd/yangtze/gec.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE default "3rdparty/blobs/southbridge/amd/yangtze/gec.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE
depends on HUDSON_GEC_FWM depends on HUDSON_GEC_FWM
@ -185,7 +179,7 @@ config ACPI_ENABLE_THERMAL_ZONE
bool bool
default y default y
endif # SOUTHBRIDGE_AMD_AGESA_BOLTON || SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE endif # SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE
if SOUTHBRIDGE_AMD_AGESA_YANGTZE if SOUTHBRIDGE_AMD_AGESA_YANGTZE
config AZ_PIN config AZ_PIN

10
src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h
View File

@ -21,7 +21,7 @@
* into the FCH PCI_INTR 0xC00/0xC01 interrupt * into the FCH PCI_INTR 0xC00/0xC01 interrupt
* routing table * routing table
*/ */
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
#define FCH_INT_TABLE_SIZE 0x54 #define FCH_INT_TABLE_SIZE 0x54
#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
#define FCH_INT_TABLE_SIZE 0x42 #define FCH_INT_TABLE_SIZE 0x42
@ -51,8 +51,8 @@
#define PIRQ_FC 0x14 /* FC */ #define PIRQ_FC 0x14 /* FC */
#define PIRQ_GEC 0x15 /* GEC */ #define PIRQ_GEC 0x15 /* GEC */
#define PIRQ_PMON 0x16 /* Performance Monitor */ #define PIRQ_PMON 0x16 /* Performance Monitor */
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
#define PIRQ_SD 0x17 /* SD */ #define PIRQ_SD 0x17 /* SD */
#endif #endif
#define PIRQ_IMC0 0x20 /* IMC INT0 */ #define PIRQ_IMC0 0x20 /* IMC INT0 */
#define PIRQ_IMC1 0x21 /* IMC INT1 */ #define PIRQ_IMC1 0x21 /* IMC INT1 */
@ -70,9 +70,7 @@
#define PIRQ_IDE 0x40 /* IDE 14h.1 */ #define PIRQ_IDE 0x40 /* IDE 14h.1 */
#define PIRQ_SATA 0x41 /* SATA 11h.0 */ #define PIRQ_SATA 0x41 /* SATA 11h.0 */
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
#define PIRQ_SD 0x42 /* SD 14h.7 */ #define PIRQ_SD 0x42 /* SD 14h.7 */
#endif
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
#define PIRQ_GPP0 0x50 /* GPP INT 0 */ #define PIRQ_GPP0 0x50 /* GPP INT 0 */
#define PIRQ_GPP1 0x51 /* GPP INT 1 */ #define PIRQ_GPP1 0x51 /* GPP INT 1 */
#define PIRQ_GPP2 0x52 /* GPP INT 2 */ #define PIRQ_GPP2 0x52 /* GPP INT 2 */

2
src/southbridge/amd/agesa/hudson/amd_pci_int_types.h
View File

@ -16,7 +16,7 @@
#ifndef AMD_PCI_INT_TYPES_H #ifndef AMD_PCI_INT_TYPES_H
#define AMD_PCI_INT_TYPES_H #define AMD_PCI_INT_TYPES_H
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
const char *intr_types[] = { const char *intr_types[] = {
[0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t",
[0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",

11
src/southbridge/amd/agesa/hudson/pci_devs.h
View File

@ -26,13 +26,6 @@
#define XHCI_DEVID 0x7814 #define XHCI_DEVID 0x7814
#define XHCI_DEVFN PCI_DEVFN(XHCI_DEV,XHCI_FUNC) #define XHCI_DEVFN PCI_DEVFN(XHCI_DEV,XHCI_FUNC)
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON)
#define XHCI2_DEV 0x10
#define XHCI2_FUNC 1
#define XHCI2_DEVID 0x7814
#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV,XHCI2_FUNC)
#endif
/* SATA */ /* SATA */
#define SATA_DEV 0x11 #define SATA_DEV 0x11
#define SATA_FUNC 0 #define SATA_FUNC 0
@ -75,7 +68,7 @@
#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) #define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC)
/* IDE */ /* IDE */
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
#define IDE_DEV 0x14 #define IDE_DEV 0x14
#define IDE_FUNC 1 #define IDE_FUNC 1
# define IDE_DEVID 0x780C # define IDE_DEVID 0x780C
@ -108,7 +101,7 @@
#define SD_DEVFN PCI_DEVFN(SD_DEV,SD_FUNC) #define SD_DEVFN PCI_DEVFN(SD_DEV,SD_FUNC)
/* PCIe Ports */ /* PCIe Ports */
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
#define SB_PCIE_DEV 0x15 #define SB_PCIE_DEV 0x15
#define SB_PCIE_PORT1_FUNC 0 #define SB_PCIE_PORT1_FUNC 0
#define SB_PCIE_PORT2_FUNC 1 #define SB_PCIE_PORT2_FUNC 1

1
src/southbridge/amd/common/Makefile.inc
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@ -1,6 +1,5 @@
ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += amd_pci_util.c
ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += amd_pci_util.c
ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) += amd_pci_util.c
ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += amd_pci_util.c
ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += amd_pci_util.c
ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += amd_pci_util.c