AGESA/binaryPI: Drop invalid AMD_AGESA_BOLTON
I refused bolton under agesa/ once it turned out to be blobbed. We have AMD_PI_BOLTON. Change-Id: Ic3cb9ada2d4f14b49f6ad54c58e6b950a1732b70 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -98,7 +98,6 @@ void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save);
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#define HAS_AGESA_FCH_OEM_CALLOUT \
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IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) || \
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IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) || \
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IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || \
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IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) || \
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IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) || \
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IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN)
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@ -13,6 +13,5 @@
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# GNU General Public License for more details.
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#
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subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) += hudson
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subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += hudson
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subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += hudson
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@ -13,16 +13,13 @@
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## GNU General Public License for more details.
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##
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config SOUTHBRIDGE_AMD_AGESA_BOLTON
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bool
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config SOUTHBRIDGE_AMD_AGESA_HUDSON
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bool
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config SOUTHBRIDGE_AMD_AGESA_YANGTZE
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bool
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if SOUTHBRIDGE_AMD_AGESA_BOLTON || SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE
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if SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE
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config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy
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def_bool y
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@ -76,21 +73,18 @@ config HUDSON_GEC_FWM
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config HUDSON_XHCI_FWM_FILE
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string "XHCI firmware path and filename"
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default "3rdparty/blobs/southbridge/amd/bolton/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_BOLTON
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default "3rdparty/blobs/southbridge/amd/hudson/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON
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default "3rdparty/blobs/southbridge/amd/yangtze/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE
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depends on HUDSON_XHCI_FWM
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config HUDSON_IMC_FWM_FILE
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string "IMC firmware path and filename"
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default "3rdparty/blobs/southbridge/amd/bolton/imc.bin" if SOUTHBRIDGE_AMD_AGESA_BOLTON
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default "3rdparty/blobs/southbridge/amd/hudson/imc.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON
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default "3rdparty/blobs/southbridge/amd/yangtze/imc.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE
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depends on HUDSON_IMC_FWM
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config HUDSON_GEC_FWM_FILE
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string "GEC firmware path and filename"
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default "3rdparty/blobs/southbridge/amd/bolton/gec.bin" if SOUTHBRIDGE_AMD_AGESA_BOLTON
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default "3rdparty/blobs/southbridge/amd/hudson/gec.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON
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default "3rdparty/blobs/southbridge/amd/yangtze/gec.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE
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depends on HUDSON_GEC_FWM
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@ -185,7 +179,7 @@ config ACPI_ENABLE_THERMAL_ZONE
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bool
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default y
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endif # SOUTHBRIDGE_AMD_AGESA_BOLTON || SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE
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endif # SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE
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if SOUTHBRIDGE_AMD_AGESA_YANGTZE
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config AZ_PIN
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@ -21,7 +21,7 @@
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* into the FCH PCI_INTR 0xC00/0xC01 interrupt
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* routing table
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*/
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#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
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#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
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#define FCH_INT_TABLE_SIZE 0x54
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#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
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#define FCH_INT_TABLE_SIZE 0x42
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@ -51,7 +51,7 @@
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#define PIRQ_FC 0x14 /* FC */
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#define PIRQ_GEC 0x15 /* GEC */
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#define PIRQ_PMON 0x16 /* Performance Monitor */
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#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
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#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
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#define PIRQ_SD 0x17 /* SD */
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#endif
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#define PIRQ_IMC0 0x20 /* IMC INT0 */
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@ -71,8 +71,6 @@
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#define PIRQ_SATA 0x41 /* SATA 11h.0 */
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#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
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#define PIRQ_SD 0x42 /* SD 14h.7 */
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#endif
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#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
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#define PIRQ_GPP0 0x50 /* GPP INT 0 */
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#define PIRQ_GPP1 0x51 /* GPP INT 1 */
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#define PIRQ_GPP2 0x52 /* GPP INT 2 */
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@ -16,7 +16,7 @@
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#ifndef AMD_PCI_INT_TYPES_H
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#define AMD_PCI_INT_TYPES_H
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#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
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#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
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const char *intr_types[] = {
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[0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t",
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[0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",
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@ -26,13 +26,6 @@
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#define XHCI_DEVID 0x7814
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#define XHCI_DEVFN PCI_DEVFN(XHCI_DEV,XHCI_FUNC)
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#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON)
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#define XHCI2_DEV 0x10
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#define XHCI2_FUNC 1
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#define XHCI2_DEVID 0x7814
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#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV,XHCI2_FUNC)
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#endif
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/* SATA */
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#define SATA_DEV 0x11
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#define SATA_FUNC 0
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@ -75,7 +68,7 @@
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#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC)
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/* IDE */
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#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
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#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
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#define IDE_DEV 0x14
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#define IDE_FUNC 1
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# define IDE_DEVID 0x780C
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@ -108,7 +101,7 @@
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#define SD_DEVFN PCI_DEVFN(SD_DEV,SD_FUNC)
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/* PCIe Ports */
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#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
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#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
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#define SB_PCIE_DEV 0x15
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#define SB_PCIE_PORT1_FUNC 0
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#define SB_PCIE_PORT2_FUNC 1
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@ -1,6 +1,5 @@
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ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += amd_pci_util.c
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ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += amd_pci_util.c
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ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) += amd_pci_util.c
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ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += amd_pci_util.c
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ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += amd_pci_util.c
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ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += amd_pci_util.c
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