drop extra whitespace at end of line for i945 + ICH7 (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4538 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
Stefan Reinauer
parent
fd4519b5ef
commit
109ab317e7
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@ -1,6 +1,6 @@
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/*
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* This file is part of the coreboot project.
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*
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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@ -29,7 +29,7 @@ Device (PDRC)
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// This does not seem to work correctly yet - set values statically for
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// now.
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//Name (PDRS, ResourceTemplate() {
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// Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, RCRB) // RCBA
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// Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, MCHB) // MCHBAR
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@ -26,7 +26,7 @@ Name(_CID,EISAID("PNP0A03")) // PCI
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Device (MCHC)
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{
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Name(_ADR, 0x00000000) // 0:0.0
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OperationRegion(MCHP, PCI_Config, 0x00, 0x100)
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Field (MCHP, DWordAcc, NoLock, Preserve)
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{
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@ -101,7 +101,7 @@ Device (GFX0)
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/* Some error happened, but we have to return something */
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Return (Package() {0x00000400})
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}
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Device(DD01)
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{
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/* Device Unique ID */
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@ -136,7 +136,7 @@ Device (GFX0)
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/* Device Set State */
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Method(_DSS, 1)
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{
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/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
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/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
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* display switch was completed
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*/
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If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
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@ -179,7 +179,7 @@ Device (GFX0)
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/* Device Set State */
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Method(_DSS, 1)
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{
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/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
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/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
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* display switch was completed
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*/
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If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
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@ -223,7 +223,7 @@ Device (GFX0)
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/* Device Set State */
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Method(_DSS, 1)
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{
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/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
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/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
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* display switch was completed
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*/
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If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
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@ -267,7 +267,7 @@ Device (GFX0)
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/* Device Set State */
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Method(_DSS, 1)
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{
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/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
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/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
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* display switch was completed
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*/
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If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
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@ -311,7 +311,7 @@ Device (GFX0)
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/* Device Set State */
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Method(_DSS, 1)
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{
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/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
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/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
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* display switch was completed
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*/
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If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
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@ -39,7 +39,7 @@ static void gma_func1_init(struct device *dev)
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/* IGD needs to be Bus Master, also enable IO accesss */
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reg32 = pci_read_config32(dev, PCI_COMMAND);
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pci_write_config32(dev, PCI_COMMAND, reg32 |
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pci_write_config32(dev, PCI_COMMAND, reg32 |
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PCI_COMMAND_MASTER | PCI_COMMAND_IO);
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}
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@ -290,7 +290,7 @@
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#define PORTARB 0x100 /* 256bit */
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/*
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/*
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* DMIBAR
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*/
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@ -43,7 +43,7 @@ int get_pcie_bar(u32 *base, u32 *len)
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dev = dev_find_slot(0, PCI_DEVFN(0, 0));
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if (!dev)
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return 0;
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pciexbar_reg = pci_read_config32(dev, 0x48);
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if (!(pciexbar_reg & (1 << 0)))
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@ -78,12 +78,12 @@ int add_northbridge_resources(struct lb_memory *mem)
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u32 pcie_config_base, pcie_config_size;
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printk_debug("Adding UMA memory area\n");
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lb_add_memory_range(mem, LB_MEM_RESERVED,
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lb_add_memory_range(mem, LB_MEM_RESERVED,
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uma_memory_base, uma_memory_size);
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printk_debug("Adding PCIe config bar\n");
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get_pcie_bar(&pcie_config_base, &pcie_config_size);
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lb_add_memory_range(mem, LB_MEM_RESERVED,
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lb_add_memory_range(mem, LB_MEM_RESERVED,
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pcie_config_base, pcie_config_size);
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return 0;
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@ -19,7 +19,7 @@
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static int bios_reset_detected(void)
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{
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/* For now ...
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/* For now ...
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* DO NOT, I repeat, DO NOT remove this. If you don't like the
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* situation, implement this instead.
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*/
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@ -24,7 +24,7 @@
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Name(\PICM, 0) // IOAPIC/8259
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Name(\DSEN, 1) // Display Output Switching Enable
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/* Global ACPI memory region. This region is used for passing information
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/* Global ACPI memory region. This region is used for passing information
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* between coreboot (aka "the system bios"), ACPI, and the SMI handler.
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* Since we don't know where this will end up in memory at ACPI compile time,
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* we have to fix it up in coreboot's ACPI creation phase.
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@ -108,7 +108,7 @@ Scope(\)
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Offset(0x1000), // Chipset
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Offset(0x3000), // Legacy Configuration Registers
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Offset(0x3404), // High Performance Timer Configuration
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HPAS, 2, // Address Select
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HPAS, 2, // Address Select
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, 5,
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HPTE, 1, // Address Enable
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Offset(0x3418), // FD (Function Disable)
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@ -135,7 +135,7 @@ Scope(\)
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RP5D, 1, // Root Port 5 disable
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RP6D, 1 // Root Port 6 disable
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}
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}
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// 0:1b.0 High Definition Audio (Azalia)
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@ -33,7 +33,7 @@ Device (AUD0)
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Device (MODM)
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{
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Name (_ADR, 0x001e0003)
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Name (_PRW, Package(){ 5, 4 })
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}
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@ -28,7 +28,7 @@ Device (HDEF)
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Name (_ADR, 0x001b0000)
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// Power Resources for Wake
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Name (_PRW, Package(){
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Name (_PRW, Package(){
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5, // Bit 5 of GPE
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4 // Can wake from S4 state.
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})
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@ -36,7 +36,7 @@ Device (LNKA)
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IRQ(Level, ActiveLow, Shared)
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{ 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 }
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})
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// Current Resource Settings for this link
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Method (_CRS, 0, Serialized)
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{
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@ -95,7 +95,7 @@ Device (LNKB)
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IRQ(Level, ActiveLow, Shared)
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{ 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 }
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})
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// Current Resource Settings for this link
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Method (_CRS, 0, Serialized)
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{
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@ -154,7 +154,7 @@ Device (LNKC)
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IRQ(Level, ActiveLow, Shared)
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{ 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 }
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})
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// Current Resource Settings for this link
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Method (_CRS, 0, Serialized)
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{
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@ -213,7 +213,7 @@ Device (LNKD)
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IRQ(Level, ActiveLow, Shared)
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{ 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 }
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})
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// Current Resource Settings for this link
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Method (_CRS, 0, Serialized)
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{
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@ -272,7 +272,7 @@ Device (LNKE)
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IRQ(Level, ActiveLow, Shared)
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{ 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 }
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})
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// Current Resource Settings for this link
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Method (_CRS, 0, Serialized)
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{
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@ -331,7 +331,7 @@ Device (LNKF)
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IRQ(Level, ActiveLow, Shared)
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{ 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 }
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})
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// Current Resource Settings for this link
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Method (_CRS, 0, Serialized)
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{
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@ -390,7 +390,7 @@ Device (LNKG)
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IRQ(Level, ActiveLow, Shared)
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{ 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 }
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})
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// Current Resource Settings for this link
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Method (_CRS, 0, Serialized)
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{
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@ -449,7 +449,7 @@ Device (LNKH)
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IRQ(Level, ActiveLow, Shared)
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{ 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 }
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})
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// Current Resource Settings for this link
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Method (_CRS, 0, Serialized)
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{
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@ -24,7 +24,7 @@
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Device (LPCB)
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{
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Name(_ADR, 0x001f0000)
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OperationRegion(LPC0, PCI_Config, 0x00, 0x100)
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Field (LPC0, AnyAcc, NoLock, Preserve)
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{
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@ -52,7 +52,7 @@ Device (LPCB)
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}
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Include ("../../../southbridge/intel/i82801gx/acpi/ich7_irqlinks.asl")
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Include ("acpi/ec.asl")
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Device (DMAC) // DMA Controller
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@ -41,7 +41,7 @@ Device (PATA)
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CreateDwordField (PBUF, 4, DMA0)
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CreateDwordField (PBUF, 8, PIO1)
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CreateDwordField (PBUF, 12, DMA1)
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CreateDwordField (PBUF, 16, FLAG)
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CreateDwordField (PBUF, 16, FLAG)
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// TODO fill return structure
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@ -55,7 +55,7 @@ Device (PATA)
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CreateDwordField (Arg0, 4, DMA0)
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CreateDwordField (Arg0, 8, PIO1)
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CreateDwordField (Arg0, 12, DMA1)
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CreateDwordField (Arg0, 16, FLAG)
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CreateDwordField (Arg0, 16, FLAG)
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// TODO: Do the deed
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}
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@ -64,7 +64,7 @@ Device (PCIB)
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// TODO: How many slots, where?
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// PCI Interrupt Routing.
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// If PICM is set, interrupts are routed over the i8259, otherwise
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// If PICM is set, interrupts are routed over the i8259, otherwise
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// over the IOAPIC. (Really? If they're above 15 they need to be routed
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// fixed over the IOAPIC?)
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@ -44,7 +44,7 @@ Device (SATA)
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CreateDwordField (PBUF, 4, DMA0)
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CreateDwordField (PBUF, 8, PIO1)
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CreateDwordField (PBUF, 12, DMA1)
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CreateDwordField (PBUF, 16, FLAG)
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CreateDwordField (PBUF, 16, FLAG)
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// TODO fill return structure
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@ -58,7 +58,7 @@ Device (SATA)
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CreateDwordField (Arg0, 4, DMA0)
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CreateDwordField (Arg0, 8, PIO1)
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CreateDwordField (Arg0, 12, DMA1)
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CreateDwordField (Arg0, 16, FLAG)
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CreateDwordField (Arg0, 16, FLAG)
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// TODO: Do the deed
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}
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@ -24,7 +24,7 @@
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Device (SBUS)
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{
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Name (_ADR, 0x001f0003)
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OperationRegion (SMBP, PCI_Config, 0x00, 0x100)
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Field(SMBP, DWordAcc, NoLock, Preserve)
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{
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@ -102,7 +102,7 @@ Device (SBUS)
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Store (0, Local0) // We're ready
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}
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}
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Store (4000, Local0) // Timeout 200ms (50us * 4000)
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While (Local0) {
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If (And (HSTS, 0x01)) { // Host Busy?
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@ -26,7 +26,7 @@
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Device (USB1)
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{
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Name(_ADR, 0x001d0000)
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OperationRegion(U01P, PCI_Config, 0, 256)
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Field(U01P, DWordAcc, NoLock, Preserve)
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{
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@ -35,7 +35,7 @@ Device (USB1)
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}
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Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake
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Method (_PSW, 1) // Power State Wake method
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{
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// USB Controller can wake OS from Sleep State
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@ -65,7 +65,7 @@ Device (USB1)
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Device (USB2)
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{
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Name(_ADR, 0x001d0001)
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OperationRegion(U02P, PCI_Config, 0, 256)
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Field(U02P, DWordAcc, NoLock, Preserve)
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{
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@ -74,7 +74,7 @@ Device (USB2)
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}
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Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake
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Method (_PSW, 1) // Power State Wake method
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{
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// USB Controller can wake OS from Sleep State
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@ -105,7 +105,7 @@ Device (USB2)
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Device (USB3)
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{
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Name(_ADR, 0x001d0002)
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OperationRegion(U03P, PCI_Config, 0, 256)
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Field(U03P, DWordAcc, NoLock, Preserve)
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{
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@ -114,7 +114,7 @@ Device (USB3)
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}
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Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake
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Method (_PSW, 1) // Power State Wake method
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{
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// USB Controller can wake OS from Sleep State
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@ -145,7 +145,7 @@ Device (USB3)
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Device (USB4)
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{
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Name(_ADR, 0x001d0003)
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OperationRegion(U04P, PCI_Config, 0, 256)
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Field(U04P, DWordAcc, NoLock, Preserve)
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{
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@ -154,7 +154,7 @@ Device (USB4)
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}
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Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake
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Method (_PSW, 1) // Power State Wake method
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{
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// USB Controller can wake OS from Sleep State
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@ -185,9 +185,9 @@ Device (USB4)
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Device (EHC1)
|
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{
|
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Name(_ADR, 0x001d0007)
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|
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|
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Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake
|
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// Leave USB ports on for to allow Wake from USB
|
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Method(_S3D,0) // Highest D State in S3 State
|
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|
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@ -109,11 +109,11 @@ extern void i82801gx_enable(device_t dev);
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#define HST_EN (1 << 0)
|
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|
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/* SMBus I/O bits.
|
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* It does not matter where we put the SMBus I/O base, as long as we
|
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* It does not matter where we put the SMBus I/O base, as long as we
|
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* keep it consistent and don't interfere with other devices. Stage2
|
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* will relocate this anyways.
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* Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE
|
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* again. But handling static BARs is a generic problem that should be
|
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* again. But handling static BARs is a generic problem that should be
|
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* solved in the device allocator.
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*/
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#define SMBUS_IO_BASE 0x0400
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@ -145,7 +145,7 @@ static void ac97_audio_init(struct device *dev)
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printk_debug("No primary codec. Disabling AC'97 Audio.\n");
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return;
|
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}
|
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|
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|
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ac97_semaphore();
|
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|
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/* Detect if codec is programmable */
|
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|
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@ -45,8 +45,8 @@ static int set_bits(u8 * port, u32 mask, u32 val)
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reg32 |= val;
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writel(reg32, port);
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|
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/* Wait for readback of register to
|
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* match what was just written to it
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/* Wait for readback of register to
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* match what was just written to it
|
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*/
|
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count = 50;
|
||||
do {
|
||||
|
|
@ -67,11 +67,11 @@ static int codec_detect(u8 * base)
|
|||
u32 reg32;
|
||||
|
||||
/* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */
|
||||
if (set_bits(base + 0x08, 1, 0) == -1)
|
||||
if (set_bits(base + 0x08, 1, 0) == -1)
|
||||
goto no_codec;
|
||||
|
||||
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
|
||||
if (set_bits(base + 0x08, 1, 1) == -1)
|
||||
if (set_bits(base + 0x08, 1, 1) == -1)
|
||||
goto no_codec;
|
||||
|
||||
/* Read in Codec location (BAR + 0xe)[2..0]*/
|
||||
|
|
@ -79,7 +79,7 @@ static int codec_detect(u8 * base)
|
|||
reg32 &= 0x0f;
|
||||
if (!reg32)
|
||||
goto no_codec;
|
||||
|
||||
|
||||
return reg32;
|
||||
|
||||
no_codec:
|
||||
|
|
@ -161,7 +161,7 @@ static u32 cim_verb_data[] = {
|
|||
static unsigned find_verb(struct device *dev, u32 viddid, u32 ** verb)
|
||||
{
|
||||
config_t *config = dev->chip_info;
|
||||
|
||||
|
||||
if (config == NULL) {
|
||||
printk_err("\ni82801gx_azalia: Not mentioned in mainboard's Config.lb!\n");
|
||||
return 0;
|
||||
|
|
@ -309,7 +309,7 @@ static void azalia_init(struct device *dev)
|
|||
|
||||
// VCi Resource Control
|
||||
reg32 = pci_mmio_read_config32(dev, 0x120);
|
||||
reg32 |= (1 << 31);
|
||||
reg32 |= (1 << 31);
|
||||
reg32 |= (1 << 24); // VCi ID
|
||||
reg32 |= (0x80 << 0); // VCi map
|
||||
pci_mmio_write_config32(dev, 0x120, reg32);
|
||||
|
|
|
|||
|
|
@ -73,7 +73,7 @@ static void i82801gx_enable_apic(struct device *dev)
|
|||
volatile u32 *ioapic_index = (volatile u32 *)0xfec00000;
|
||||
volatile u32 *ioapic_data = (volatile u32 *)0xfec00010;
|
||||
|
||||
/* Enable ACPI I/O and power management.
|
||||
/* Enable ACPI I/O and power management.
|
||||
* Set SCI IRQ to IRQ9
|
||||
*/
|
||||
pci_write_config8(dev, ACPI_CNTL, 0x80);
|
||||
|
|
@ -275,7 +275,7 @@ static void i82801gx_power_options(device_t dev)
|
|||
reg32 = inl(pmbase + 0x04); // PM1_CNT
|
||||
#if CONFIG_HAVE_ACPI_RESUME
|
||||
acpi_slp_type = (((reg32 >> 10) & 7) == 5) ? 3 : 0;
|
||||
printk_debug("PM1_CNT: 0x%08x --> acpi_sleep_type: %x\n",
|
||||
printk_debug("PM1_CNT: 0x%08x --> acpi_sleep_type: %x\n",
|
||||
reg32, acpi_slp_type);
|
||||
#endif
|
||||
reg32 |= (1 << 1); // enable C3->C0 transition on bus master
|
||||
|
|
@ -286,7 +286,7 @@ static void i82801gx_power_options(device_t dev)
|
|||
static void i82801gx_configure_cstates(device_t dev)
|
||||
{
|
||||
u8 reg8;
|
||||
|
||||
|
||||
reg8 = pci_read_config8(dev, 0xa9); // Cx state configuration
|
||||
reg8 |= (1 << 4) | (1 << 3) | (1 << 2); // Enable Popup & Popdown
|
||||
pci_write_config8(dev, 0xa9, reg8);
|
||||
|
|
@ -318,7 +318,7 @@ static void i82801gx_rtc_init(struct device *dev)
|
|||
static void enable_hpet(void)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
|
||||
/* Move HPET to default address 0xfed00000 and enable it */
|
||||
reg32 = RCBA32(0x3404);
|
||||
reg32 |= (1 << 7); // HPET Address Enable
|
||||
|
|
@ -329,7 +329,7 @@ static void enable_hpet(void)
|
|||
static void enable_clock_gating(void)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
|
||||
/* Enable Clock Gating for most devices */
|
||||
reg32 = RCBA32(0x341c);
|
||||
reg32 |= (1 << 31); // LPC clock gating
|
||||
|
|
@ -360,7 +360,7 @@ static void i82801gx_lock_smm(struct device *dev)
|
|||
outb(0x1e, 0xb2); // Disable ACPI mode
|
||||
printk_debug("done.\n");
|
||||
#endif
|
||||
/* Don't allow evil boot loaders, kernels, or
|
||||
/* Don't allow evil boot loaders, kernels, or
|
||||
* userspace applications to deceive us:
|
||||
*/
|
||||
smm_lock();
|
||||
|
|
|
|||
|
|
@ -71,10 +71,10 @@ static void ich_pci_dev_enable_resources(struct device *dev)
|
|||
ops = ops_pci(dev);
|
||||
if (dev->on_mainboard && ops && ops->set_subsystem) {
|
||||
printk_debug("%s subsystem <- %02x/%02x\n",
|
||||
dev_path(dev),
|
||||
dev_path(dev),
|
||||
CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
|
||||
CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
|
||||
ops->set_subsystem(dev,
|
||||
ops->set_subsystem(dev,
|
||||
CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
|
||||
CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
|
||||
}
|
||||
|
|
@ -82,7 +82,7 @@ static void ich_pci_dev_enable_resources(struct device *dev)
|
|||
command = pci_read_config16(dev, PCI_COMMAND);
|
||||
command |= dev->command;
|
||||
#ifdef PCI_BRIDGE_UPDATE_COMMAND
|
||||
/* If we write to PCI_COMMAND, on some systems
|
||||
/* If we write to PCI_COMMAND, on some systems
|
||||
* this will cause the ROM and APICs not being visible
|
||||
* anymore.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@ static void pci_init(struct device *dev)
|
|||
u32 reg32;
|
||||
|
||||
printk_debug("Initializing ICH7 PCIe bridge.\n");
|
||||
|
||||
|
||||
/* Enable Bus Master */
|
||||
reg32 = pci_read_config32(dev, PCI_COMMAND);
|
||||
reg32 |= PCI_COMMAND_MASTER;
|
||||
|
|
|
|||
|
|
@ -132,26 +132,26 @@ static void sata_init(struct device *dev)
|
|||
/* Set Interrupt Line */
|
||||
/* Interrupt Pin is set by D31IP.PIP */
|
||||
pci_write_config8(dev, INTR_LN, 0xff);
|
||||
|
||||
|
||||
/* Set timings */
|
||||
pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
|
||||
IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
|
||||
IDE_PPE0 | IDE_IE0 | IDE_TIME0);
|
||||
pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
|
||||
IDE_SITRE | IDE_ISP_3_CLOCKS |
|
||||
IDE_SITRE | IDE_ISP_3_CLOCKS |
|
||||
IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);
|
||||
|
||||
|
||||
/* Sync DMA */
|
||||
pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0);
|
||||
pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
|
||||
|
||||
|
||||
/* Set IDE I/O Configuration */
|
||||
reg32 = SIG_MODE_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
|
||||
pci_write_config32(dev, IDE_CONFIG, reg32);
|
||||
|
||||
|
||||
/* Port 0 & 1 enable XXX */
|
||||
pci_write_config8(dev, 0x92, 0x15);
|
||||
|
||||
|
||||
/* SATA Initialization register */
|
||||
pci_write_config32(dev, 0x94, 0x1a000180);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@
|
|||
#include <arch/io.h>
|
||||
#include "i82801gx.h"
|
||||
#include "i82801gx_smbus.h"
|
||||
|
||||
|
||||
#define SMB_BASE 0x20
|
||||
static void smbus_init(struct device *dev)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -81,17 +81,17 @@ extern unsigned int smm_len;
|
|||
static u16 pmbase = DEFAULT_PMBASE;
|
||||
|
||||
/**
|
||||
* @brief read and clear PM1_STS
|
||||
* @brief read and clear PM1_STS
|
||||
* @return PM1_STS register
|
||||
*/
|
||||
static u16 reset_pm1_status(void)
|
||||
{
|
||||
u16 reg16;
|
||||
|
||||
|
||||
reg16 = inw(pmbase + PM1_STS);
|
||||
/* set status bits are cleared by writing 1 to them */
|
||||
outw(reg16, pmbase + PM1_STS);
|
||||
|
||||
|
||||
return reg16;
|
||||
}
|
||||
|
||||
|
|
@ -110,17 +110,17 @@ static void dump_pm1_status(u16 pm1_sts)
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief read and clear SMI_STS
|
||||
* @brief read and clear SMI_STS
|
||||
* @return SMI_STS register
|
||||
*/
|
||||
static u32 reset_smi_status(void)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
|
||||
reg32 = inl(pmbase + SMI_STS);
|
||||
/* set status bits are cleared by writing 1 to them */
|
||||
outl(reg32, pmbase + SMI_STS);
|
||||
|
||||
|
||||
return reg32;
|
||||
}
|
||||
|
||||
|
|
@ -158,11 +158,11 @@ static void dump_smi_status(u32 smi_sts)
|
|||
static u32 reset_gpe0_status(void)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
|
||||
reg32 = inl(pmbase + GPE0_STS);
|
||||
/* set status bits are cleared by writing 1 to them */
|
||||
outl(reg32, pmbase + GPE0_STS);
|
||||
|
||||
|
||||
return reg32;
|
||||
}
|
||||
|
||||
|
|
@ -191,20 +191,20 @@ static void dump_gpe0_status(u32 gpe0_sts)
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief read and clear TCOx_STS
|
||||
* @brief read and clear TCOx_STS
|
||||
* @return TCOx_STS registers
|
||||
*/
|
||||
static u32 reset_tco_status(void)
|
||||
{
|
||||
u32 tcobase = pmbase + 0x60;
|
||||
u32 reg32;
|
||||
|
||||
|
||||
reg32 = inl(tcobase + 0x04);
|
||||
/* set status bits are cleared by writing 1 to them */
|
||||
outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS
|
||||
if (reg32 & (1 << 18))
|
||||
outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS
|
||||
|
||||
|
||||
return reg32;
|
||||
}
|
||||
|
||||
|
|
@ -236,7 +236,7 @@ static void dump_tco_status(u32 tco_sts)
|
|||
static void smi_set_eos(void)
|
||||
{
|
||||
u8 reg8;
|
||||
|
||||
|
||||
reg8 = inb(pmbase + SMI_EN);
|
||||
reg8 |= EOS;
|
||||
outb(reg8, pmbase + SMI_EN);
|
||||
|
|
@ -286,8 +286,8 @@ void smm_relocate(void)
|
|||
* - Writes to io 0xb2 (APMC)
|
||||
* - Writes to the Local Apic ICR with Delivery mode SMI.
|
||||
*
|
||||
* Using the local apic is a bit more tricky. According to
|
||||
* AMD Family 11 Processor BKDG no destination shorthand must be
|
||||
* Using the local apic is a bit more tricky. According to
|
||||
* AMD Family 11 Processor BKDG no destination shorthand must be
|
||||
* used.
|
||||
* The whole SMM initialization is quite a bit hardware specific, so
|
||||
* I'm not too worried about the better of the methods at the moment
|
||||
|
|
|
|||
|
|
@ -102,17 +102,17 @@ void *tcg = (void *)0x0;
|
|||
void *smi1 = (void *)0x0;
|
||||
|
||||
/**
|
||||
* @brief read and clear PM1_STS
|
||||
* @brief read and clear PM1_STS
|
||||
* @return PM1_STS register
|
||||
*/
|
||||
static u16 reset_pm1_status(void)
|
||||
{
|
||||
u16 reg16;
|
||||
|
||||
|
||||
reg16 = inw(pmbase + PM1_STS);
|
||||
/* set status bits are cleared by writing 1 to them */
|
||||
outw(reg16, pmbase + PM1_STS);
|
||||
|
||||
|
||||
return reg16;
|
||||
}
|
||||
|
||||
|
|
@ -131,17 +131,17 @@ static void dump_pm1_status(u16 pm1_sts)
|
|||
}
|
||||
|
||||
/**
|
||||
* @brief read and clear SMI_STS
|
||||
* @brief read and clear SMI_STS
|
||||
* @return SMI_STS register
|
||||
*/
|
||||
static u32 reset_smi_status(void)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
|
||||
reg32 = inl(pmbase + SMI_STS);
|
||||
/* set status bits are cleared by writing 1 to them */
|
||||
outl(reg32, pmbase + SMI_STS);
|
||||
|
||||
|
||||
return reg32;
|
||||
}
|
||||
|
||||
|
|
@ -179,11 +179,11 @@ static void dump_smi_status(u32 smi_sts)
|
|||
static u32 reset_gpe0_status(void)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
|
||||
reg32 = inl(pmbase + GPE0_STS);
|
||||
/* set status bits are cleared by writing 1 to them */
|
||||
outl(reg32, pmbase + GPE0_STS);
|
||||
|
||||
|
||||
return reg32;
|
||||
}
|
||||
|
||||
|
|
@ -213,20 +213,20 @@ static void dump_gpe0_status(u32 gpe0_sts)
|
|||
|
||||
|
||||
/**
|
||||
* @brief read and clear TCOx_STS
|
||||
* @brief read and clear TCOx_STS
|
||||
* @return TCOx_STS registers
|
||||
*/
|
||||
static u32 reset_tco_status(void)
|
||||
{
|
||||
u32 tcobase = pmbase + 0x60;
|
||||
u32 reg32;
|
||||
|
||||
|
||||
reg32 = inl(tcobase + 0x04);
|
||||
/* set status bits are cleared by writing 1 to them */
|
||||
outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS
|
||||
if (reg32 & (1 << 18))
|
||||
outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS
|
||||
|
||||
|
||||
return reg32;
|
||||
}
|
||||
|
||||
|
|
@ -296,7 +296,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
|
|||
u8 reg8;
|
||||
u32 reg32;
|
||||
u8 slp_typ;
|
||||
/* FIXME: the power state on boot should be read from
|
||||
/* FIXME: the power state on boot should be read from
|
||||
* CMOS or even better from GNVS. Right now it's hard
|
||||
* coded at compile time.
|
||||
*/
|
||||
|
|
@ -347,7 +347,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
|
|||
}
|
||||
|
||||
/* Write back to the SLP register to cause the originally intended
|
||||
* event again. We need to set BIT13 (SLP_EN) though to make the
|
||||
* event again. We need to set BIT13 (SLP_EN) though to make the
|
||||
* sleep happen.
|
||||
*/
|
||||
outl(reg32 | SLP_EN, pmbase + PM1_CNT);
|
||||
|
|
@ -545,7 +545,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st
|
|||
#undef IOTRAP
|
||||
}
|
||||
|
||||
typedef void (*smi_handler)(unsigned int node,
|
||||
typedef void (*smi_handler)(unsigned int node,
|
||||
smm_state_save_area_t *state_save);
|
||||
|
||||
smi_handler southbridge_smi[32] = {
|
||||
|
|
@ -580,7 +580,7 @@ smi_handler southbridge_smi[32] = {
|
|||
NULL, // [28] reserved
|
||||
NULL, // [29] reserved
|
||||
NULL, // [30] reserved
|
||||
NULL // [31] reserved
|
||||
NULL // [31] reserved
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -601,14 +601,14 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
|
|||
* happening in the following calls.
|
||||
*/
|
||||
smi_sts = reset_smi_status();
|
||||
|
||||
|
||||
/* Filter all non-enabled SMI events */
|
||||
// FIXME Double check, this clears MONITOR
|
||||
// smi_sts &= inl(pmbase + SMI_EN);
|
||||
|
||||
/* Call SMI sub handler for each of the status bits */
|
||||
for (i = 0; i < 31; i++) {
|
||||
if (smi_sts & (1 << i)) {
|
||||
if (smi_sts & (1 << i)) {
|
||||
if (southbridge_smi[i])
|
||||
southbridge_smi[i](node, state_save);
|
||||
else {
|
||||
|
|
|
|||
Loading…
Reference in New Issue