soc/intel/common/timer: Move USE_LEGACY_8254_TIMER into common/block/timer
This patch moves USE_LEGACY_8254_TIMER Kconfig into common/block/timer for better code sharing. Also ported CB:33512 for SPT and ICP PCH. Change-Id: Ic767ff97aaa3eb7fa35ffa38fa416d006eaa6e78 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -316,14 +316,6 @@ config SOC_INTEL_CANNONLAKE_DEBUG_CONSENT
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Setting non-zero value will allow to use DBC or DCI to debug SOC.
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Setting non-zero value will allow to use DBC or DCI to debug SOC.
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PlatformDebugConsent in FspmUpd.h has the details.
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PlatformDebugConsent in FspmUpd.h has the details.
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config USE_LEGACY_8254_TIMER
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bool "Use Legacy 8254 Timer"
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default y if PAYLOAD_SEABIOS
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default n
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help
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This sets the Enable8254ClockGating UPD, which according to the FSP Integration
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guide needs to be disabled in order to boot SeaBIOS, but should otherwise be enabled.
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config PRERAM_CBMEM_CONSOLE_SIZE
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config PRERAM_CBMEM_CONSOLE_SIZE
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hex
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hex
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default 0xe00
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default 0xe00
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@ -2,3 +2,13 @@ config SOC_INTEL_COMMON_BLOCK_TIMER
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bool
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bool
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help
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help
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Intel Processor common TIMER support
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Intel Processor common TIMER support
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config USE_LEGACY_8254_TIMER
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bool "Use Legacy 8254 Timer"
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default y if PAYLOAD_SEABIOS || VGA_ROM_RUN
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default n
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help
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This sets the FSP UPD to enable Legacy 8254 clock gating. As per
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the FSP Integration guide Legacy 8254 timer clock gating UPD needs
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to be disabled in order to boot SeaBIOS or run OpRom,
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but should otherwise be enabled.
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@ -204,8 +204,6 @@ struct soc_intel_icelake_config {
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/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
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/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
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uint8_t eist_enable;
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uint8_t eist_enable;
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/* Statically clock gate 8254 PIT. */
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uint8_t clock_gate_8254;
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/* Enable C6 DRAM */
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/* Enable C6 DRAM */
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uint8_t enable_c6dram;
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uint8_t enable_c6dram;
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/*
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/*
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@ -199,16 +199,6 @@ static void pch_misc_init(void)
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outb((1 << 7), 0x70);
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outb((1 << 7), 0x70);
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};
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};
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static void clock_gate_8254(const struct device *dev)
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{
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const config_t *config = dev->chip_info;
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if (!config->clock_gate_8254)
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return;
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itss_clock_gate_8254();
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}
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void lpc_soc_init(struct device *dev)
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void lpc_soc_init(struct device *dev)
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{
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{
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/* Legacy initialization */
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/* Legacy initialization */
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@ -229,7 +219,6 @@ void lpc_soc_init(struct device *dev)
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soc_pch_pirq_init(dev);
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soc_pch_pirq_init(dev);
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setup_i8259();
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setup_i8259();
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i8259_configure_irq_trigger(9, 1);
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i8259_configure_irq_trigger(9, 1);
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clock_gate_8254(dev);
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soc_mirror_dmi_pcr_io_dec();
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soc_mirror_dmi_pcr_io_dec();
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}
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}
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@ -124,6 +124,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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/* disable Legacy PME */
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/* disable Legacy PME */
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memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
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memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
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/* Legacy 8254 timer support */
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params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
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params->Enable8254ClockGatingOnS3 = 1;
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/* S0ix */
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/* S0ix */
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params->PchPmSlpS0Enable = config->s0ix_enable;
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params->PchPmSlpS0Enable = config->s0ix_enable;
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@ -237,6 +237,9 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
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params->SlowSlewRateForSa = config->SlowSlewRateForSa;
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params->SlowSlewRateForSa = config->SlowSlewRateForSa;
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params->FastPkgCRampDisable = config->FastPkgCRampDisable;
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params->FastPkgCRampDisable = config->FastPkgCRampDisable;
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/* Legacy 8254 timer support */
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params->Early8254ClockGatingEnable = !CONFIG_USE_LEGACY_8254_TIMER;
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soc_irq_settings(params);
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soc_irq_settings(params);
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}
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}
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@ -513,9 +513,6 @@ struct soc_intel_skylake_config {
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/* Enable/Disable host reads to PMC XRAM registers */
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/* Enable/Disable host reads to PMC XRAM registers */
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u8 PchPmPmcReadDisable;
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u8 PchPmPmcReadDisable;
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/* Statically clock gate 8254 PIT. */
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u8 clock_gate_8254;
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/*
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/*
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* Use SD card detect GPIO with default config:
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* Use SD card detect GPIO with default config:
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* - Edge triggered
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* - Edge triggered
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@ -315,6 +315,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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/* disable Legacy PME */
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/* disable Legacy PME */
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memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
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memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
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/* Legacy 8254 timer support */
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params->Early8254ClockGatingEnable = !CONFIG_USE_LEGACY_8254_TIMER;
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memcpy(params->SerialIoDevMode, config->SerialIoDevMode,
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memcpy(params->SerialIoDevMode, config->SerialIoDevMode,
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sizeof(params->SerialIoDevMode));
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sizeof(params->SerialIoDevMode));
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@ -96,16 +96,6 @@ static const struct reg_script pch_misc_init_script[] = {
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REG_SCRIPT_END
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REG_SCRIPT_END
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};
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};
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static void clock_gate_8254(struct device *dev)
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{
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const config_t *config = dev->chip_info;
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if (!config->clock_gate_8254)
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return;
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itss_clock_gate_8254();
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}
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void lpc_soc_init(struct device *dev)
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void lpc_soc_init(struct device *dev)
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{
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{
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const config_t *const config = dev->chip_info;
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const config_t *const config = dev->chip_info;
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@ -125,5 +115,4 @@ void lpc_soc_init(struct device *dev)
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soc_pch_pirq_init(dev);
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soc_pch_pirq_init(dev);
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setup_i8259();
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setup_i8259();
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i8259_configure_irq_trigger(9, 1);
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i8259_configure_irq_trigger(9, 1);
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clock_gate_8254(dev);
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}
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}
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