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nb/amd/mct_ddr3: Train correct receiver in TrainDQSRdWrPos_D_Fam15 

Change-Id: Ia26950a8297f0a7125c21e995c89a3fc68d9d8a9
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13932
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Timothy Pearson 2016-03-07 13:29:24 -06:00 committed by Martin Roth
parent ed85f614b0
commit 10d6fceaa0
1 changed files with 1 additions and 4 deletions
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5
src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
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@ -1342,14 +1342,11 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat,
Errors = 0;
dual_rank = 0;
Receiver = mct_InitReceiver_D(pDCTstat, dct);
if (receiver_start > Receiver)
Receiver = receiver_start;
/* There are four receiver pairs, loosely associated with chipselects.
* This is essentially looping over each rank within each DIMM.
*/
for (; Receiver < receiver_end; Receiver++) {
for (Receiver = receiver_start; Receiver < receiver_end; Receiver++) {
dimm = (Receiver >> 1);
if ((Receiver & 0x1) == 0) {
/* Even rank of DIMM */