diff --git a/src/mainboard/google/brya/variants/anraggar/gpio.c b/src/mainboard/google/brya/variants/anraggar/gpio.c
index b01bc2c674..40505bde59 100644
--- a/src/mainboard/google/brya/variants/anraggar/gpio.c
+++ b/src/mainboard/google/brya/variants/anraggar/gpio.c
@@ -71,6 +71,11 @@ static const struct pad_config override_gpio_table[] = {
 
 /* Early pad configuration in bootblock */
 static const struct pad_config early_gpio_table[] = {
+	/* C0  : SMBCLK ==> EN_PP3300_TCHSCR_X */
+	PAD_CFG_GPO(GPP_C0, 1, DEEP),
+	/* C1  : SMBDATA ==> TCHSCR_RST_L */
+	PAD_CFG_GPO(GPP_C1, 1, DEEP),
+
 	/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
 	PAD_CFG_GPO(GPP_H20, 0, DEEP),
 	/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb
index 30c3c1b3b0..5308317922 100644
--- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb
+++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb
@@ -221,10 +221,10 @@ chip soc/intel/alderlake
 				register "generic.detect" = "1"
 				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
 				register "generic.reset_delay_ms" = "200"
-				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C6)"
 				register "generic.enable_delay_ms" = "12"
-				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C6)"
-				register "generic.stop_off_delay_ms" = "2"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
+				register "generic.stop_off_delay_ms" = "200"
 				register "generic.has_power_resource" = "1"
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 41 on end