mb/clevo/tgl-u: add new board L14xMU
Add new board Clevo L14xMU (TGL).
GPIOs were configured based on schematics.
Tested and working:
- On-board RAM (M471A1G44AB0-CWE)
- DIMM slot (tested Crucial CT16G4SFD8266.16FJ1 / MTA16ATF2G64HZ-2G6J1)
- Graphics (GOP driver), including HDMI
- Keyboard
- I2C touchpad (including interrupt)
- TPM (with interrupt on Windows, only polling on Linux [1])
- microSD Card reader
- both NVME ports
- Speakers
- Microphone
- Camera
- WLAN/BT (CNVi)
- All USB2/3 ports including Type-C
- Thunderbolt detects my work laptop in TB Control Center
(I couldn't test anything more due to security policy.)
- TianoCore
- internal flashing with flashrom on vendor firmware
Note on TPM:
The vendor sets Intel PTT to default-on in newer CSME images, which
conflicts with the dTPM. Currently, there are two ways to make it work:
1) Boot vendor firmware once to let it disable PTT via CSME firmware
feature override.
2) Use Intel Flash Image Tool (FIT) to set "initial power-up state" to
disabled.
Boots fine:
- Debian testing, unstable (Linux 5.16.14, 5.17.0-rc6)
- Windows 10 21H2 (Build 19044.1586)
Untested:
- Thunderbolt (see above)
- Type-C DisplayPort
- S-ATA
Doesn't work:
- TPM interrupt on Linux [1]
- All EC related functions - EC driver is WIP
- WLAN/BT (PCIe) - gets detected but can't be enabled
- 3G/LTE (not powered without EC driver)
- Fn-Keys
- S0ix
- UCSI
- Fan control
- Battery info
[1] https://lkml.org/lkml/2021/5/1/103
Change-Id: I4c4bef3827da10241e9b01e12ecc4276e131a620
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Michael Niewöhner
parent
422fdceaa8
commit
10e47d80cb
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@ -0,0 +1,63 @@
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config BOARD_CLEVO_TGLU_COMMON
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def_bool n
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select BOARD_ROMSIZE_KB_16384
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select DRIVERS_I2C_HID
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select DRIVERS_INTEL_PMC
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select DRIVERS_INTEL_USB4_RETIMER
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select HAVE_ACPI_TABLES
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select HAVE_CMOS_DEFAULT
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select HAVE_OPTION_TABLE
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select INTEL_GMA_HAVE_VBT
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_LPC_TPM
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select MAINBOARD_HAS_TPM2
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select NO_UART_ON_SUPERIO
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select SOC_INTEL_COMMON_BLOCK_HDA_VERB
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select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
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select SOC_INTEL_TIGERLAKE
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select SPD_READ_BY_WORD
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select SYSTEM_TYPE_LAPTOP
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config BOARD_CLEVO_L140MU
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select BOARD_CLEVO_TGLU_COMMON
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select HAVE_SPD_IN_CBFS
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if BOARD_CLEVO_TGLU_COMMON
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config MAINBOARD_DIR
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default "clevo/tgl-u"
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config VARIANT_DIR
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default "l140mu" if BOARD_CLEVO_L140MU
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config MAINBOARD_PART_NUMBER
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default "L140MU" if BOARD_CLEVO_L140MU
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config MAINBOARD_VERSION
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default "2.2A" if BOARD_CLEVO_L140MU
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config DEVICETREE
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default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
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config CBFS_SIZE
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default 0xb00000 if BOARD_CLEVO_L140MU
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config CONSOLE_POST
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default y
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config UART_FOR_CONSOLE
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default 2
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config TPM_PIRQ
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default 0x77 if BOARD_CLEVO_L140MU # GPP_C9_IRQ
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config POST_DEVICE
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default n
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config SEABIOS_PS2_TIMEOUT
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default 500
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config USE_PM_ACPI_TIMER
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default n
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endif
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@ -0,0 +1,4 @@
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comment "Tiger Lake U"
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config BOARD_CLEVO_L140MU
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bool "L140MU / L141MU / L142MU"
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@ -0,0 +1,14 @@
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
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bootblock-y += bootblock.c
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bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
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romstage-y += romstage.c
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romstage-y += variants/$(VARIANT_DIR)/romstage.c
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ramstage-y += ramstage.c
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ramstage-y += variants/$(VARIANT_DIR)/ramstage.c
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ramstage-y += variants/$(VARIANT_DIR)/gpio.c
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ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
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subdirs-y += variants/$(VARIANT_DIR)
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@ -0,0 +1,6 @@
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Vendor name: Clevo
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Category: laptop
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ROM package: SOIC-8
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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@ -0,0 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <variant/gpio.h>
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void bootblock_mainboard_early_init(void)
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{
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variant_configure_early_gpios();
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}
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@ -0,0 +1,3 @@
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boot_option=Fallback
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debug_level=Debug
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power_on_after_fail=Disable
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@ -0,0 +1,57 @@
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# SPDX-License-Identifier: GPL-2.0-only
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# -----------------------------------------------------------------
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entries
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# start-bit length config config-ID name
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0 120 r 0 reserved_memory
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# -----------------------------------------------------------------
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 4 boot_option
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388 4 h 0 reboot_counter
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# -----------------------------------------------------------------
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# coreboot config options: console
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395 4 e 6 debug_level
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# -----------------------------------------------------------------
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# coreboot config options: southbridge
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410 2 e 7 power_on_after_fail
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# -----------------------------------------------------------------
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# vboot nv area
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800 128 r 0 vbnv
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# -----------------------------------------------------------------
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# coreboot config options: check sums
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984 16 h 0 check_sum
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# -----------------------------------------------------------------
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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6 0 Emergency
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6 1 Alert
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6 2 Critical
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6 3 Error
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6 4 Warning
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6 5 Notice
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6 6 Info
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6 7 Debug
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6 8 Spew
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7 0 Disable
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7 1 Enable
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7 2 Keep
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# -----------------------------------------------------------------
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checksums
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checksum 392 799 984
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@ -0,0 +1,32 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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ACPI_DSDT_REV_2,
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20110725
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)
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{
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#include <acpi/dsdt_top.asl>
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#include <soc/intel/common/block/acpi/acpi/platform.asl>
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#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
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#include <cpu/intel/common/acpi/cpu.asl>
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Device (\_SB.PCI0)
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{
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#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
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#include <soc/intel/tigerlake/acpi/southbridge.asl>
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#include <soc/intel/tigerlake/acpi/tcss.asl>
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#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
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}
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Scope (\_SB.PCI0.LPCB)
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{
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#include <drivers/pc80/pc/ps2_controller.asl>
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}
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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}
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@ -0,0 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef VARIANT_GPIO_H
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#define VARIANT_GPIO_H
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void variant_configure_early_gpios(void);
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void variant_configure_gpios(void);
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#endif
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@ -0,0 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef VARIANT_RAMSTAGE_H
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#define VARIANT_RAMSTAGE_H
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void variant_configure_fsps(FSP_S_CONFIG *params);
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#endif
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef VARIANT_ROMSTAGE_H
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#define VARIANT_ROMSTAGE_H
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void variant_configure_fspm(FSPM_UPD *memupd);
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#endif
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/device.h>
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#include <soc/ramstage.h>
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#include <variant/gpio.h>
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#include <variant/ramstage.h>
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void mainboard_silicon_init_params(FSP_S_CONFIG *params)
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{
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variant_configure_fsps(params);
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}
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static void init_mainboard(void *chip_info)
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{
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variant_configure_gpios();
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}
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struct chip_operations mainboard_ops = {
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.init = init_mainboard,
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};
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <soc/romstage.h>
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#include <variant/romstage.h>
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void mainboard_memory_init_params(FSPM_UPD *memupd)
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{
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variant_configure_fspm(memupd);
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}
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@ -0,0 +1,32 @@
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23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00
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00 00 05 0D F8 FF 01 00 6E 6E 6E 11 00 6E F0 0A
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20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35
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16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 E8 F5
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0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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80 CE 00 00 00 00 00 00 00 4D 34 37 31 41 31 47
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34 34 41 42 30 2D 43 57 45 20 20 20 20 00 80 CE
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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@ -0,0 +1 @@
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SPD_SOURCES = samsung-M471A1G44AB0-CWE
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@ -0,0 +1,2 @@
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Board name: L140MU
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Release year: 2021
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Binary file not shown.
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@ -0,0 +1,249 @@
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chip soc/intel/tigerlake
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device cpu_cluster 0 on
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register "tcc_offset" = "12"
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register "eist_enable" = "true"
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device lapic 0 on end
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end
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device domain 0 on
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subsystemid 0x1558 0x14a1 inherit
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device ref system_agent on
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register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{
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.tdp_pl1_override = 20,
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.tdp_pl2_override = 30,
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.psys_pmax = 65,
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}"
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register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{
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.tdp_pl1_override = 20,
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.tdp_pl2_override = 30,
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.psys_pmax = 65,
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}"
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register "SaGv" = "SaGv_Enabled"
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register "enable_c6dram" = "true"
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end
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device ref igpu on
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register "gfx" = "GMA_DEFAULT_PANEL(0)"
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# eDP
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register "DdiPortAConfig" = "1"
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register "DdiPortAHpd" = "1"
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register "DdiPortADdc" = "0"
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# HDMI
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register "DdiPortBConfig" = "0"
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register "DdiPortBHpd" = "1"
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register "DdiPortBDdc" = "1"
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end
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device ref dptf on end
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device ref tbt_pcie_rp0 on end
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device ref tbt_dma0 on
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chip drivers/intel/usb4/retimer
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register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)"
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use tcss_usb3_port1 as dfp[0].typec_port
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device generic 0 on end
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end
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end
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device ref north_xhci on
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register "UsbTcPortEn" = "true"
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register "TcssXhciEn" = "true"
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chip drivers/usb/acpi
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device ref tcss_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB3 J_TYPEC1""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "group" = "ACPI_PLD_GROUP(1, 1)"
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device ref tcss_usb3_port1 on end
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end
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end
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end
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end
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device ref south_xhci on
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# USB2
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register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A, left (J_USB3_1)
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register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A, right (J_USB3_2)
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register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C (J_TYPEC1)
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register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # 3G/LTE
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register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Camera
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register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
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# USB3
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, left (J_USB3_1)
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, right (J_USB3_2)
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 3G/LTE
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# ACPI
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chip drivers/usb/acpi
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device ref xhci_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB2 J_USB3_1""
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register "type" = "UPC_TYPE_A"
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register "group" = "ACPI_PLD_GROUP(1, 2)"
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device ref usb2_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 J_USB3_2""
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register "type" = "UPC_TYPE_A"
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register "group" = "ACPI_PLD_GROUP(2, 1)"
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device ref usb2_port2 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 J_TYPEC1""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "group" = "ACPI_PLD_GROUP(1, 1)"
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device ref usb2_port3 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 3G/LTE""
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register "type" = "UPC_TYPE_INTERNAL"
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device ref usb2_port4 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Camera""
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register "type" = "UPC_TYPE_INTERNAL"
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device ref usb2_port7 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Bluetooth""
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register "type" = "UPC_TYPE_INTERNAL"
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device ref usb2_port10 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 J_USB3_1""
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register "type" = "UPC_TYPE_A"
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register "group" = "ACPI_PLD_GROUP(1, 1)"
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device ref usb3_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 J_USB3_2""
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register "type" = "UPC_TYPE_A"
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register "group" = "ACPI_PLD_GROUP(2, 1)"
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device ref usb3_port2 on end
|
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end
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chip drivers/usb/acpi
|
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register "desc" = ""USB3 3G/LTE""
|
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register "type" = "UPC_TYPE_INTERNAL"
|
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device ref usb3_port4 on end
|
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end
|
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end
|
||||
end
|
||||
end
|
||||
device ref i2c0 on
|
||||
register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
|
||||
register "common_soc_config.i2c[0]" = "{
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 80,
|
||||
.fall_time_ns = 110,
|
||||
.speed_config[0] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.scl_lcnt = 0x13b,
|
||||
.scl_hcnt = 0xc8,
|
||||
.sda_hold = 0x5a,
|
||||
}
|
||||
}"
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""ELAN040D""
|
||||
register "generic.desc" = ""ELAN Touchpad""
|
||||
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)"
|
||||
register "generic.probed" = "true"
|
||||
register "hid_desc_reg_offset" = "0x01"
|
||||
device i2c 15 on end
|
||||
end
|
||||
end
|
||||
device ref i2c1 on # Retimer ROM
|
||||
register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
|
||||
end
|
||||
device ref cnvi_wifi on
|
||||
register "CnviBtCore" = "true"
|
||||
chip drivers/wifi/generic
|
||||
register "wake" = "GPE0_PME_B0"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref pcie_rp3 on
|
||||
register "PcieRpEnable[2]" = "true"
|
||||
register "PcieRpLtrEnable[2]" = "true"
|
||||
register "PcieClkSrcUsage[1]" = "2"
|
||||
register "PcieClkSrcClkReq[1]" = "1"
|
||||
register "PcieRpSlotImplemented[2]" = "true"
|
||||
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
|
||||
chip drivers/wifi/generic
|
||||
device pci 00.0 on end
|
||||
end
|
||||
end
|
||||
device ref pcie_rp6 on
|
||||
# Card reader
|
||||
device pci 00.0 on end
|
||||
register "PcieRpEnable[5]" = "true"
|
||||
register "PcieRpLtrEnable[5]" = "true"
|
||||
register "PcieClkSrcUsage[2]" = "5"
|
||||
register "PcieClkSrcClkReq[2]" = "2"
|
||||
end
|
||||
device ref pcie_rp9 on
|
||||
# SSD2 - PCIe mode
|
||||
register "PcieRpEnable[8]" = "true"
|
||||
register "PcieRpLtrEnable[8]" = "true"
|
||||
register "PcieClkSrcUsage[0]" = "8"
|
||||
register "PcieClkSrcClkReq[0]" = "0"
|
||||
register "PcieRpSlotImplemented[8]" = "true"
|
||||
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
device generic 0 on end
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D9)"
|
||||
register "srcclk_pin" = "0"
|
||||
end
|
||||
end
|
||||
device ref peg on
|
||||
# SSD1 - PCIe4
|
||||
register "PcieClkSrcUsage[3]" = "0x40"
|
||||
register "PcieClkSrcClkReq[3]" = "3"
|
||||
#register "CpuPcieRpLtrEnable[0]" = "true" # currently set in ramstage.c
|
||||
#register "CpuPcieRpSlotImplemented[0]" = "true" # currently set in ramstage.c
|
||||
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
device generic 0 on end
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C13)"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C22)"
|
||||
register "srcclk_pin" = "3"
|
||||
end
|
||||
end
|
||||
device ref pch_espi on
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0c31.0 on end
|
||||
end
|
||||
end
|
||||
device ref sata on
|
||||
# SSD2 - SATA mode
|
||||
register "SataPortsEnable[1]" = "true"
|
||||
register "SataPortsDevSlp[1]" = "true"
|
||||
register "SataPortsEnableDitoConfig[1]" = "true"
|
||||
register "SataSalpSupport" = "true"
|
||||
end
|
||||
device ref pmc hidden
|
||||
register "AcousticNoiseMitigation" = "true"
|
||||
register "SlowSlewRate" = "SLEW_FAST_4"
|
||||
register "FastPkgCRampDisable" = "true"
|
||||
register "PchPmSlpS3MinAssert" = "3" # 50ms
|
||||
register "PchPmSlpS4MinAssert" = "1" # 1s
|
||||
register "PchPmSlpAMinAssert" = "4" # 2s
|
||||
register "PchPmSlpSusMinAssert" = "4" # 4s
|
||||
register "PchPmPwrCycDur" = "0" # 4-5s
|
||||
register "s0ix_enable" = "true"
|
||||
chip drivers/intel/pmc_mux
|
||||
device generic 0 on
|
||||
chip drivers/intel/pmc_mux/conn
|
||||
use usb2_port3 as usb2_port
|
||||
use tcss_usb3_port1 as usb3_port
|
||||
device generic 0 alias conn0 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref hda on
|
||||
register "PchHdaAudioLinkHdaEnable" = "true"
|
||||
end
|
||||
device ref uart2 on
|
||||
register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"
|
||||
end
|
||||
device ref heci1 on end
|
||||
device ref smbus on end
|
||||
device ref shared_ram on end
|
||||
device ref p2sb hidden end
|
||||
device ref fast_spi on end
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,235 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <variant/gpio.h>
|
||||
|
||||
/* Name format: <pad name> / <net/pin name in schematics> */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
/* ------- GPIO Group GPD ------- */
|
||||
PAD_NC(GPD0, NONE),
|
||||
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), /* ACPRESENT / AC_PRESENT */
|
||||
PAD_NC(GPD2, NONE),
|
||||
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* PWRBTN# / PWR_BTN# */
|
||||
PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SLP_S3# / SUSB#_PCH */
|
||||
PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SLP_S4# / SUSC#_PCH */
|
||||
PAD_NC(GPD6, NONE),
|
||||
PAD_NC(GPD7, NONE),
|
||||
PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUSCLK / SUS_CLK */
|
||||
PAD_NC(GPD9, NONE),
|
||||
PAD_NC(GPD10, NONE),
|
||||
PAD_NC(GPD11, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_A ------- */
|
||||
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), /* ESPI_IO0 / ESPI_IO_0 */
|
||||
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), /* ESPI_IO1 / ESPI_IO_1 */
|
||||
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), /* ESPI_IO2 / ESPI_IO_2 */
|
||||
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), /* ESPI_IO3 / ESPI_IO_3 */
|
||||
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* ESPI_CS# / ESPI_CS_N */
|
||||
PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), /* ESPI_CLK */
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* ESPI_RESET# / ESPI_RESET_N */
|
||||
PAD_NC(GPP_A7, NONE),
|
||||
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2), /* CNV_RF_RESET# / CNVI_RST# */
|
||||
PAD_CFG_NF(GPP_A9, UP_20K, DEEP, NF2), /* MODEM_CLKREQ / CNVI_CLKREQ */
|
||||
PAD_NC(GPP_A10, NONE),
|
||||
PAD_NC(GPP_A11, NONE),
|
||||
PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), /* SATAXPCIE1 / SATAGP1 (wrong name!) */
|
||||
PAD_CFG_GPO(GPP_A13, 1, DEEP), /* GPP_A13 / PCH_BT_EN */
|
||||
PAD_NC(GPP_A14, NONE),
|
||||
PAD_NC(GPP_A15, NONE),
|
||||
PAD_NC(GPP_A16, NONE),
|
||||
PAD_NC(GPP_A17, NONE),
|
||||
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* DDSP_HPDB / HDMI_HPD */
|
||||
PAD_NC(GPP_A19, NONE),
|
||||
PAD_NC(GPP_A20, NONE),
|
||||
PAD_NC(GPP_A21, NONE),
|
||||
PAD_NC(GPP_A22, NONE),
|
||||
PAD_CFG_GPO(GPP_A23, 0, PLTRST), /* GPP_A23 / TC_RETIMER_FORCE_PWR */
|
||||
|
||||
/* ------- GPIO Group GPP_B ------- */
|
||||
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* CORE_VID0 / VCCIN_AUX_VID0 */
|
||||
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* CORE_VID1 / VCCIN_AUX_VID1 */
|
||||
PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), /* VRALERT# */
|
||||
PAD_CFG_GPI_APIC_LOW(GPP_B3, NONE, DEEP), /* GPP_B3 (touchpad interrupt) */
|
||||
PAD_NC(GPP_B4, NONE),
|
||||
PAD_NC(GPP_B5, NONE),
|
||||
PAD_NC(GPP_B6, NONE),
|
||||
PAD_NC(GPP_B7, NONE),
|
||||
PAD_NC(GPP_B8, NONE),
|
||||
PAD_NC(GPP_B9, NONE),
|
||||
PAD_NC(GPP_B10, NONE),
|
||||
PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* GPP_B11 / TBTA_I2C_INT */
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* SLP_S0# */
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PLT_RST# */
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPKR / PCH_SPKR */
|
||||
PAD_NC(GPP_B15, NONE),
|
||||
PAD_NC(GPP_B16, NONE),
|
||||
PAD_NC(GPP_B17, NONE),
|
||||
PAD_NC(GPP_B18, NONE),
|
||||
PAD_NC(GPP_B19, NONE),
|
||||
PAD_NC(GPP_B20, NONE),
|
||||
PAD_NC(GPP_B21, NONE),
|
||||
PAD_NC(GPP_B22, NONE),
|
||||
PAD_NC(GPP_B23, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_C ------- */
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMBCLK / SMB_CLK_DDR */
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBDATA / SMB_DAT_DDR */
|
||||
PAD_NC(GPP_C2, NONE),
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0CLK */
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_DATA */
|
||||
PAD_NC(GPP_C5, NONE),
|
||||
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1CLK / TBT_I2C_SCL */
|
||||
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1_DATA / TBT_I2C_SDA */
|
||||
PAD_NC(GPP_C8, NONE),
|
||||
PAD_CFG_GPI_APIC_LOW(GPP_C9, NONE, DEEP), /* GPP_C9 / TPM_PIRQ# */
|
||||
PAD_NC(GPP_C10, NONE),
|
||||
PAD_NC(GPP_C11, NONE),
|
||||
PAD_NC(GPP_C12, NONE),
|
||||
PAD_CFG_GPO(GPP_C13, 1, DEEP), /* GPP_C13 / SSD1_PWR_DN# */
|
||||
PAD_NC(GPP_C14, NONE),
|
||||
PAD_NC(GPP_C15, NONE),
|
||||
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_SDA / T_SDA (touchpad) */
|
||||
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_SCL / T_SCL (touchpad) */
|
||||
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SDA / PCH_I2C_SDA (retimer rom) */
|
||||
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* I2C1_SCL / PCH_I2C_SCL (retimer rom) */
|
||||
PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1), /* UART2_RXD */
|
||||
PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1), /* UART2_TXD */
|
||||
PAD_CFG_GPO(GPP_C22, 1, DEEP), /* GPP_C22 / GPP_C12_RTD3 (SSD1) */
|
||||
PAD_NC(GPP_C23, UP_20K), /* GPP_C23 / PCH_GPP_C23 (WLAN_WAKEUP#) */
|
||||
|
||||
/* ------- GPIO Group GPP_D ------- */
|
||||
PAD_CFG_GPO(GPP_D0, 1, DEEP), /* GPP_D0 / SB_BLON */
|
||||
PAD_NC(GPP_D1, NONE),
|
||||
PAD_NC(GPP_D2, NONE), /* LEDKB_DET# (unused; not sold w/o KBLED) */
|
||||
PAD_NC(GPP_D3, NONE), /* BOARD_ID (unused; always high) */
|
||||
PAD_NC(GPP_D4, NONE),
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* SRCCLKREQ0# / SSD1_CLKREQ# (for SSD2!) */
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* SRCCLKREQ1# / WLAN_CLKREQ# */
|
||||
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* SRCCLKREQ2# / CARD_CLKREQ# */
|
||||
PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* SRCCLKREQ3# / SSD2_CLKREQ# (for SSD1!) */
|
||||
PAD_CFG_GPO(GPP_D9, 1, DEEP), /* GPP_D9 / GPP_D13_RTD3 (SSD2) */
|
||||
PAD_NC(GPP_D10, NONE),
|
||||
PAD_NC(GPP_D11, NONE),
|
||||
PAD_NC(GPP_D12, NONE),
|
||||
PAD_NC(GPP_D13, NONE),
|
||||
PAD_CFG_GPO(GPP_D14, 1, DEEP), /* GPP_D14 / SSD2_PWR_DN# */
|
||||
PAD_NC(GPP_D15, NONE),
|
||||
PAD_NC(GPP_D16, NONE),
|
||||
PAD_NC(GPP_D17, NONE),
|
||||
PAD_NC(GPP_D18, NONE),
|
||||
PAD_NC(GPP_D19, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_E ------- */
|
||||
PAD_NC(GPP_E0, NONE),
|
||||
PAD_CFG_GPO(GPP_E1, 0, DEEP), /* GPP_E1 / ROM_I2C_EN */
|
||||
PAD_NC(GPP_E2, NONE),
|
||||
PAD_NC(GPP_E3, NONE), /* SB_KBCRST# (eSPI Virtual Wire) */
|
||||
PAD_NC(GPP_E4, NONE),
|
||||
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1 */
|
||||
PAD_NC(GPP_E6, NONE),
|
||||
PAD_NC(GPP_E7, NONE),
|
||||
PAD_NC(GPP_E8, NONE),
|
||||
PAD_NC(GPP_E9, NONE),
|
||||
PAD_NC(GPP_E10, NONE),
|
||||
PAD_NC(GPP_E11, NONE),
|
||||
PAD_NC(GPP_E12, NONE),
|
||||
PAD_NC(GPP_E13, NONE),
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDSP_HPDA / EDP_HPD */
|
||||
PAD_NC(GPP_E15, NONE), /* SCI# (eSPI Virtual Wire) */
|
||||
PAD_NC(GPP_E16, NONE), /* SMI# (eSPI Virtual Wire) */
|
||||
PAD_NC(GPP_E17, NONE),
|
||||
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF2), /* TBT_LSX0_TXD */
|
||||
PAD_CFG_NF(GPP_E19, NONE, DEEP, NF2), /* TBT_LSX0_RXD */
|
||||
PAD_NC(GPP_E20, NONE), /* SWI# (eSPI Virtual Wire) */
|
||||
PAD_NC(GPP_E21, NONE),
|
||||
PAD_NC(GPP_E22, NONE),
|
||||
PAD_NC(GPP_E23, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_F ------- */
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* CNV_BRI_DT / CNVI_BRI_DT */
|
||||
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), /* CNV_BRI_RSP / CNVI_BRI_RSP */
|
||||
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), /* CNV_RGI_DT / CNVI_RGI_DT */
|
||||
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), /* CNV_RGI_RSP / CNVI_RGI_RSP */
|
||||
PAD_NC(GPP_F4, NONE),
|
||||
PAD_NC(GPP_F5, NONE),
|
||||
PAD_NC(GPP_F6, NONE),
|
||||
PAD_NC(GPP_F7, NONE),
|
||||
PAD_NC(GPP_F8, NONE),
|
||||
PAD_NC(GPP_F9, NONE),
|
||||
PAD_NC(GPP_F10, NONE),
|
||||
PAD_NC(GPP_F11, NONE),
|
||||
PAD_NC(GPP_F12, NONE),
|
||||
PAD_NC(GPP_F13, NONE),
|
||||
PAD_NC(GPP_F14, NONE),
|
||||
PAD_NC(GPP_F15, NONE),
|
||||
PAD_NC(GPP_F16, NONE),
|
||||
PAD_CFG_GPI(GPP_F17, UP_20K, DEEP), /* GPP_F17 / TPM_DET# */
|
||||
PAD_NC(GPP_F18, NONE),
|
||||
PAD_NC(GPP_F19, NONE),
|
||||
PAD_NC(GPP_F20, NONE),
|
||||
PAD_NC(GPP_F21, NONE),
|
||||
PAD_NC(GPP_F22, NONE),
|
||||
PAD_NC(GPP_F23, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_H ------- */
|
||||
PAD_NC(GPP_H0, NONE),
|
||||
PAD_NC(GPP_H1, NONE),
|
||||
PAD_NC(GPP_H2, NONE),
|
||||
PAD_NC(GPP_H3, NONE),
|
||||
PAD_NC(GPP_H4, NONE),
|
||||
PAD_NC(GPP_H5, NONE),
|
||||
PAD_NC(GPP_H6, NONE),
|
||||
PAD_NC(GPP_H7, NONE),
|
||||
PAD_NC(GPP_H8, NONE),
|
||||
PAD_NC(GPP_H9, NONE),
|
||||
PAD_NC(GPP_H10, NONE),
|
||||
PAD_NC(GPP_H11, NONE),
|
||||
PAD_NC(GPP_H12, NONE),
|
||||
PAD_NC(GPP_H13, NONE),
|
||||
PAD_NC(GPP_H14, NONE),
|
||||
PAD_NC(GPP_H15, NONE),
|
||||
PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), /* DDPB_CTRLCLK / HDMI_CTRLCLK */
|
||||
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), /* DDPB_CTRLDATA / HDMI_CTRLDATA */
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* CPU_C10_GATE# */
|
||||
PAD_NC(GPP_H19, NONE), /* GPP_H19 / CNVI_WAKE#
|
||||
(UART_WAKE# in M.2 spec; unused)
|
||||
*/
|
||||
PAD_NC(GPP_H20, NONE),
|
||||
PAD_NC(GPP_H21, NONE),
|
||||
PAD_NC(GPP_H22, NONE),
|
||||
PAD_NC(GPP_H23, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_R ------- */
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), /* HDA_BCLK / HDA_BITCLK */
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), /* HDA_SYNC */
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), /* HDA_SDO / HDA_SDOUT */
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), /* HDA_SDI0 / HDA_SDIN0 */
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), /* HDA_RST# / AZ_RST#_R */
|
||||
PAD_NC(GPP_R5, NONE),
|
||||
PAD_NC(GPP_R6, NONE),
|
||||
PAD_NC(GPP_R7, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_S ------- */
|
||||
PAD_NC(GPP_S0, NONE),
|
||||
PAD_NC(GPP_S1, NONE),
|
||||
PAD_NC(GPP_S2, NONE),
|
||||
PAD_NC(GPP_S3, NONE),
|
||||
PAD_NC(GPP_S4, NONE),
|
||||
PAD_NC(GPP_S5, NONE),
|
||||
PAD_NC(GPP_S6, NONE),
|
||||
PAD_NC(GPP_S7, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_T ------- */
|
||||
PAD_NC(GPP_T2, NONE),
|
||||
PAD_NC(GPP_T3, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_U ------- */
|
||||
PAD_NC(GPP_U4, NONE),
|
||||
PAD_NC(GPP_U5, NONE),
|
||||
};
|
||||
|
||||
void variant_configure_gpios(void)
|
||||
{
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
}
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/gpio.h>
|
||||
#include <variant/gpio.h>
|
||||
|
||||
/* Name format: <pad name> / <net/pin name in schematics> */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_RXD */
|
||||
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2_TXD */
|
||||
};
|
||||
|
||||
void variant_configure_early_gpios(void)
|
||||
{
|
||||
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
|
||||
}
|
||||
|
|
@ -0,0 +1,82 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek ALC293 */
|
||||
0x10ec0293, /* Vendor ID */
|
||||
0x155814a1, /* Subsystem ID */
|
||||
12, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x155814a1),
|
||||
|
||||
/* Microphone (display lid), vendor value: 0x90a60130 */
|
||||
AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC(
|
||||
INTEGRATED,
|
||||
LOCATION_OTHER, /* vendor: SEPARATE_CHASSIS */
|
||||
SPECIAL7, /* lid, vendor: NA */
|
||||
MIC_IN,
|
||||
OTHER_DIGITAL,
|
||||
COLOR_UNKNOWN,
|
||||
1, /* no presence detect */
|
||||
3, 0)
|
||||
),
|
||||
|
||||
/* Integrated speakers, vendor value: 0x90170110 */
|
||||
AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC(
|
||||
INTEGRATED,
|
||||
LOCATION_OTHER, /* vendor: SEPARATE_CHASSIS */
|
||||
BOTTOM, /* vendor: NA */
|
||||
SPEAKER,
|
||||
OTHER_ANALOG,
|
||||
COLOR_UNKNOWN,
|
||||
1, /* no presence detect */
|
||||
1, 0)
|
||||
),
|
||||
|
||||
/* Headphones, vendor value: 0x02211020 */
|
||||
AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_DESC(
|
||||
JACK,
|
||||
EXTERNAL_PRIMARY_CHASSIS,
|
||||
RIGHT, /* vendor: FRONT */
|
||||
HP_OUT,
|
||||
STEREO_MONO_1_8,
|
||||
BLACK,
|
||||
0, /* has presence detect */
|
||||
2, 0)
|
||||
),
|
||||
|
||||
/* ext. Microphone, vendor value: 0x411111f0, linux override: 0x01a1913c */
|
||||
AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_DESC(
|
||||
JACK,
|
||||
EXTERNAL_PRIMARY_CHASSIS,
|
||||
RIGHT, /* vendor: REAR */
|
||||
MIC_IN,
|
||||
STEREO_MONO_1_8,
|
||||
BLACK, /* vendor: PINK */
|
||||
1, /* no separate presence detect */
|
||||
3, 12)
|
||||
),
|
||||
|
||||
/* PCBEEP, vendor value: 0x41748245 */
|
||||
AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_DESC(
|
||||
INTEGRATED, /* vendor: NC */
|
||||
INTERNAL, /* vendor: EXTERNAL_PRIMARY_CHASSIS */
|
||||
NA, /* vendor: REAR */
|
||||
DEVICE_OTHER, /* vendor: MODEM_HANDSET_SIDE */
|
||||
OTHER_ANALOG, /* vendor: RCA */
|
||||
COLOR_UNKNOWN, /* vendor: PURPLE */
|
||||
1, /* no presence detect, vendor: 2 */
|
||||
4, 5)
|
||||
),
|
||||
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000), /* NC, but different from 0x411111f0 */
|
||||
AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)),
|
||||
AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)),
|
||||
AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)),
|
||||
AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)),
|
||||
AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/ramstage.h>
|
||||
#include <variant/ramstage.h>
|
||||
|
||||
void variant_configure_fsps(FSP_S_CONFIG *params)
|
||||
{
|
||||
/* SSD1 - PCIe4 */
|
||||
params->CpuPcieRpLtrEnable[0] = 1;
|
||||
params->CpuPcieRpSlotImplemented[0] = 1;
|
||||
}
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/meminit.h>
|
||||
#include <variant/romstage.h>
|
||||
|
||||
void variant_configure_fspm(FSPM_UPD *memupd)
|
||||
{
|
||||
const struct mb_cfg board_cfg = {
|
||||
.type = MEM_TYPE_DDR4,
|
||||
};
|
||||
const struct mem_spd spd_info = {
|
||||
.topo = MEM_TOPO_MIXED,
|
||||
.cbfs_index = 0,
|
||||
.smbus[1] = { .addr_dimm[0] = 0x52, },
|
||||
};
|
||||
const bool half_populated = false;
|
||||
|
||||
memcfg_init(memupd, &board_cfg, &spd_info, half_populated);
|
||||
}
|
||||
Loading…
Reference in New Issue