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soc/intel/{skl,cnl,icl}: Drop soc_uart_set_legacy_mode() 

This is never called: The only calling path is guarded by both
!DRIVERS_UART_8250MEM_32 and INTEL_LPSS_UART_FOR_CONSOLE but the
latter selects the former.

If somebody figures out how this is supposed to be used, we can
easily revive the implementation.

Change-Id: I96e304bdee4eadb52725027d0d662ef75f3d4307
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33093
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nico Huber 2019-05-29 23:13:47 +02:00 committed by Patrick Georgi
parent 2deb5fb3b0
commit 10ed868d19
3 changed files with 0 additions and 45 deletions
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15
src/soc/intel/cannonlake/uart.c
View File

@ -24,10 +24,6 @@
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
/* Serial IO UART controller legacy mode */
#define PCR_SERIAL_IO_GPPRVRW7 0x618
#define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx))
const struct uart_gpio_pad_config uart_gpio_pads[] = {
{
.console_index = 0,
@ -54,17 +50,6 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = {
const int uart_max_index = ARRAY_SIZE(uart_gpio_pads);
void soc_uart_set_legacy_mode(void)
{
pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7,
PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE));
/*
* Dummy read after setting any of GPPRVRW7.
* Required for UART 16550 8-bit Legacy mode to become active
*/
lpss_clk_read(UART_BASE(CONFIG_UART_FOR_CONSOLE));
}
struct device *soc_uart_console_to_device(int uart_console)
{
/*

15
src/soc/intel/icelake/uart.c
View File

@ -24,10 +24,6 @@
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
/* Serial IO UART controller legacy mode */
#define PCR_SERIAL_IO_GPPRVRW7 0x618
#define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx))
const struct uart_gpio_pad_config uart_gpio_pads[] = {
{
.console_index = 0,
@ -54,17 +50,6 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = {
const int uart_max_index = ARRAY_SIZE(uart_gpio_pads);
void soc_uart_set_legacy_mode(void)
{
pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7,
PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE));
/*
* Dummy read after setting any of GPPRVRW7.
* Required for UART 16550 8-bit Legacy mode to become active
*/
lpss_clk_read(UART_BASE(CONFIG_UART_FOR_CONSOLE));
}
struct device *soc_uart_console_to_device(int uart_console)
{
/*

15
src/soc/intel/skylake/uart.c
View File

@ -24,10 +24,6 @@
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
/* Serial IO UART controller legacy mode */
#define PCR_SERIAL_IO_GPPRVRW7 0x618
#define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx))
/* UART pad configuration. Support RXD and TXD for now. */
const struct uart_gpio_pad_config uart_gpio_pads[] = {
{
@ -55,17 +51,6 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = {
const int uart_max_index = ARRAY_SIZE(uart_gpio_pads);
void soc_uart_set_legacy_mode(void)
{
pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7,
PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE));
/*
* Dummy read after setting any of GPPRVRW7.
* Required for UART 16550 8-bit Legacy mode to become active
*/
lpss_clk_read(UART_BASE(CONFIG_UART_FOR_CONSOLE));
}
struct device *soc_uart_console_to_device(int uart_console)
{
/*