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nb/intel/sandybridge: Define and use MMCONF_BUS_NUMBER 

Change-Id: Id88c18129bb773d979ad84bd0bb47188d74d4bc4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49762
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2021-01-20 14:58:32 +01:00
parent 32770f840d
commit 10f9b83f53
5 changed files with 21 additions and 59 deletions
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4
src/northbridge/intel/sandybridge/Kconfig
View File

@ -90,6 +90,10 @@ config MMCONF_BASE_ADDRESS
help
The MRC blob requires it to be at 0xf0000000.
config MMCONF_BUS_NUMBER
int
default 64
config DCACHE_RAM_BASE
hex
default 0xfefe0000

11
src/northbridge/intel/sandybridge/acpi.c
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@ -11,15 +11,8 @@
unsigned long acpi_fill_mcfg(unsigned long current)
{
u32 length, pciexbar;
if (!decode_pcie_bar(&pciexbar, &length))
return current;
const int max_buses = length / MiB;
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0, 0,
max_buses - 1);
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
CONFIG_MMCONF_BASE_ADDRESS, 0, 0, CONFIG_MMCONF_BUS_NUMBER - 1);
return current;
}

19
src/northbridge/intel/sandybridge/bootblock.c
View File

@ -1,13 +1,23 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/bootblock.h>
#include <assert.h>
#include <device/pci_ops.h>
#include <types.h>
#include "sandybridge.h"
static uint32_t encode_pciexbar_length(void)
{
switch (CONFIG_MMCONF_BUS_NUMBER) {
case 256: return 0 << 1;
case 128: return 1 << 1;
case 64: return 2 << 1;
default: return dead_code_t(uint32_t);
}
}
void bootblock_early_northbridge_init(void)
{
uint32_t reg;
/*
* The "io" variant of the config access is explicitly used to setup the
* PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to true. That way, all
@ -18,8 +28,7 @@ void bootblock_early_northbridge_init(void)
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
*/
reg = 0;
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, reg);
reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0);
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg);
}

44
src/northbridge/intel/sandybridge/northbridge.c
View File

@ -35,39 +35,6 @@ bool is_sandybridge(void)
static const int legacy_hole_base_k = 0xa0000 / 1024;
static const int legacy_hole_size_k = 384;
int decode_pcie_bar(u32 *const base, u32 *const len)
{
*base = 0;
*len = 0;
struct device *dev = pcidev_on_root(0, 0);
if (!dev)
return 0;
const u32 pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
/* MMCFG not supported or not enabled */
if (!(pciexbar_reg & (1 << 0)))
return 0;
switch ((pciexbar_reg >> 1) & 3) {
case 0: /* 256MB */
*base = pciexbar_reg & (0x0f << 28);
*len = 256 * MiB;
return 1;
case 1: /* 128M */
*base = pciexbar_reg & (0x1f << 27);
*len = 128 * MiB;
return 1;
case 2: /* 64M */
*base = pciexbar_reg & (0x3f << 26);
*len = 64 * MiB;
return 1;
}
return 0;
}
static const char *northbridge_acpi_name(const struct device *dev)
{
if (dev->path.type == DEVICE_PATH_DOMAIN)
@ -84,10 +51,6 @@ static const char *northbridge_acpi_name(const struct device *dev)
return NULL;
}
/*
* TODO We could determine how many PCIe busses we need in the bar.
* For now, that number is hardcoded to a max of 64.
*/
static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
@ -126,7 +89,6 @@ static void add_fixed_resources(struct device *dev, int index)
static void mc_read_resources(struct device *dev)
{
u32 pcie_config_base, pcie_config_len;
uint64_t tom, me_base, touud;
uint32_t tseg_base, uma_size, tolud;
uint16_t ggc;
@ -135,11 +97,7 @@ static void mc_read_resources(struct device *dev)
pci_dev_read_resources(dev);
if (decode_pcie_bar(&pcie_config_base, &pcie_config_len)) {
const int buses = pcie_config_len / MiB;
struct resource *resource = new_resource(dev, PCIEXBAR);
mmconf_resource_init(resource, pcie_config_base, buses);
}
mmconf_resource(dev, PCIEXBAR);
/* Total Memory 2GB example:
*

2
src/northbridge/intel/sandybridge/sandybridge.h
View File

@ -91,8 +91,6 @@ void perform_raminit(int s3resume);
void report_memory_config(void);
enum platform_type get_platform_type(void);
int decode_pcie_bar(u32 *const base, u32 *const len);
#include <device/device.h>
struct acpi_rsdp;