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sb/intel/bd82x6x: Use <device/azalia_device.h> registers 

Change-Id: I1e30dd7b300d7975e7a89fbe1e66aaf7affd1702
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44127
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS 2020-08-03 15:34:46 +02:00 committed by Patrick Georgi
parent eaf2ae764e
commit 11178bd305
1 changed files with 12 additions and 16 deletions
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28
src/southbridge/intel/bd82x6x/azalia.c
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@ -12,10 +12,6 @@
#include "chip.h" #include "chip.h"
#include "pch.h" #include "pch.h"
#define HDA_ICII_REG 0x68
#define HDA_ICII_BUSY (1 << 0)
#define HDA_ICII_VALID (1 << 1)
typedef struct southbridge_intel_bd82x6x_config config_t; typedef struct southbridge_intel_bd82x6x_config config_t;
static int set_bits(void *port, u32 mask, u32 val) static int set_bits(void *port, u32 mask, u32 val)
@ -52,15 +48,15 @@ static int codec_detect(u8 *base)
u8 reg8; u8 reg8;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
if (set_bits(base + 0x08, 1, 1) == -1) if (set_bits(base + HDA_GCTL_REG, 1, 1) == -1)
goto no_codec; goto no_codec;
/* Write back the value once reset bit is set. */ /* Write back the value once reset bit is set. */
write16(base + 0x0, write16(base + HDA_GCAP_REG,
read16(base + 0x0)); read16(base + HDA_GCAP_REG));
/* Read in Codec location (BAR + 0xe)[2..0]*/ /* Read in Codec location (BAR + 0xe)[2..0]*/
reg8 = read8(base + 0xe); reg8 = read8(base + HDA_STATESTS_REG);
reg8 &= 0x0f; reg8 &= 0x0f;
if (!reg8) if (!reg8)
goto no_codec; goto no_codec;
@ -70,7 +66,7 @@ static int codec_detect(u8 *base)
no_codec: no_codec:
/* Codec Not found */ /* Codec Not found */
/* Put HDA back in reset (BAR + 0x8) [0] */ /* Put HDA back in reset (BAR + 0x8) [0] */
set_bits(base + 0x08, 1, 0); set_bits(base + HDA_GCTL_REG, 1, 0);
printk(BIOS_DEBUG, "Azalia: No codec!\n"); printk(BIOS_DEBUG, "Azalia: No codec!\n");
return 0; return 0;
} }
@ -159,14 +155,14 @@ static void codec_init(struct device *dev, u8 *base, int addr)
} }
reg32 = (addr << 28) | 0x000f0000; reg32 = (addr << 28) | 0x000f0000;
write32(base + 0x60, reg32); write32(base + HDA_IC_REG, reg32);
if (wait_for_valid(base) == -1) { if (wait_for_valid(base) == -1) {
printk(BIOS_DEBUG, " codec not valid.\n"); printk(BIOS_DEBUG, " codec not valid.\n");
return; return;
} }
reg32 = read32(base + 0x64); reg32 = read32(base + HDA_IR_REG);
/* 2 */ /* 2 */
printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32); printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32);
@ -183,7 +179,7 @@ static void codec_init(struct device *dev, u8 *base, int addr)
if (wait_for_ready(base) == -1) if (wait_for_ready(base) == -1)
return; return;
write32(base + 0x60, verb[i]); write32(base + HDA_IC_REG, verb[i]);
if (wait_for_valid(base) == -1) if (wait_for_valid(base) == -1)
return; return;
@ -203,7 +199,7 @@ static void codecs_init(struct device *dev, u8 *base, u32 codec_mask)
if (wait_for_ready(base) == -1) if (wait_for_ready(base) == -1)
return; return;
write32(base + 0x60, pc_beep_verbs[i]); write32(base + HDA_IC_REG, pc_beep_verbs[i]);
if (wait_for_valid(base) == -1) if (wait_for_valid(base) == -1)
return; return;
@ -268,9 +264,9 @@ static void azalia_init(struct device *dev)
/* Codec Initialization Programming Sequence */ /* Codec Initialization Programming Sequence */
/* Take controller out of reset */ /* Take controller out of reset */
reg32 = read32(base + 0x08); reg32 = read32(base + HDA_GCTL_REG);
reg32 |= (1 << 0); reg32 |= HDA_GCTL_CRST;
write32(base + 0x08, reg32); write32(base + HDA_GCTL_REG, reg32);
/* Wait 1ms */ /* Wait 1ms */
udelay(1000); udelay(1000);