soc/intel/braswell/smbus: Enable early SMBus in romstage

Enable early SMBus support compatible with SPD library using Intel SB
common SMBus API.

TEST=boot Protectli FW2B with new FSP, MemoryInit should pass without
errors

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I92a2c5a6d0b38e5658cfdc017041f12717dabdd5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/soc/intel/braswell/Makefile.inc

@@ -14,6 +14,7 @@ romstage-y += iosf.c
 romstage-y += lpc_init.c
 romstage-y += memmap.c
 romstage-y += pmutil.c
+romstage-y += smbus.c
 romstage-y += tsc_freq.c
 
 postcar-y += tsc_freq.c

src/soc/intel/braswell/smbus.c

@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ * Copyright (C) 2019 3mdeb
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/early_smbus.h>
+#include <soc/iomap.h>
+#include <southbridge/intel/common/smbus.h>
+
+u8 smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset)
+{
+	return do_smbus_read_byte(SMBUS_BASE_ADDRESS, addr, offset);
+}
+
+u8 smbus_write_byte(u32 smbus_dev, u8 addr, u8 offset, u8 value)
+{
+	return do_smbus_write_byte(SMBUS_BASE_ADDRESS, addr, offset, value);
+}