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AGESA binaryPI: Fix and optimize for MAX_NODES_NUM 

With nodeid<8, CONFIG_CDB==0x18, PCI device number does
not overflow. CONFIG_CDB is not a value we can configure.

Change-Id: I23e9707a8ec12dcd80c00688d6237d085d1abf36
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
This commit is contained in:
Kyösti Mälkki 2018-05-20 20:12:32 +03:00 committed by Patrick Georgi
parent 71955a5b3f
commit 113f670baa
7 changed files with 9 additions and 104 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/northbridge/amd/agesa/family12/northbridge.c
View File

@ -46,11 +46,7 @@ static unsigned fx_devs = 0;
static struct device *get_node_pci(u32 nodeid, u32 fn)
{
if ((CONFIG_CDB + nodeid) < 32) {
return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
} else {
return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn));
}
return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
}
static void get_fx_devs(void)

6
src/northbridge/amd/agesa/family14/northbridge.c
View File

@ -46,11 +46,7 @@ static unsigned fx_devs = 0;
static struct device *get_node_pci(u32 nodeid, u32 fn)
{
if ((CONFIG_CDB + nodeid) < 32) {
return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
} else {
return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn));
}
return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
}
static void get_fx_devs(void)

21
src/northbridge/amd/agesa/family15tn/northbridge.c
View File

@ -40,7 +40,7 @@
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#define MAX_NODE_NUMS (MAX_NODES * MAX_DIES)
#define MAX_NODE_NUMS MAX_NODES
typedef struct dram_base_mask {
u32 base; //[47:27] at [28:8]
@ -102,15 +102,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
static struct device *get_node_pci(u32 nodeid, u32 fn)
{
#if MAX_NODE_NUMS + CONFIG_CDB >= 32
if ((CONFIG_CDB + nodeid) < 32) {
return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
} else {
return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn));
}
#else
return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
#endif
}
static void get_fx_devs(void)
@ -153,18 +145,7 @@ static void f1_write_config32(unsigned reg, u32 value)
static u32 amdfam15_nodeid(struct device *dev)
{
#if MAX_NODE_NUMS == 64
unsigned busn;
busn = dev->bus->secondary;
if (busn != CONFIG_CBB) {
return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32;
} else {
return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
}
#else
return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
#endif
}
static void set_vga_enable_reg(u32 nodeid, u32 linkn)

21
src/northbridge/amd/agesa/family16kb/northbridge.c
View File

@ -39,7 +39,7 @@
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#define MAX_NODE_NUMS (MAX_NODES * MAX_DIES)
#define MAX_NODE_NUMS MAX_NODES
typedef struct dram_base_mask {
u32 base; //[47:27] at [28:8]
@ -101,15 +101,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
static struct device *get_node_pci(u32 nodeid, u32 fn)
{
#if MAX_NODE_NUMS + CONFIG_CDB >= 32
if ((CONFIG_CDB + nodeid) < 32) {
return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
} else {
return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn));
}
#else
return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
#endif
}
static void get_fx_devs(void)
@ -152,18 +144,7 @@ static void f1_write_config32(unsigned reg, u32 value)
static u32 amdfam16_nodeid(struct device *dev)
{
#if MAX_NODE_NUMS == 64
unsigned busn;
busn = dev->bus->secondary;
if (busn != CONFIG_CBB) {
return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32;
} else {
return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
}
#else
return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
#endif
}
static void set_vga_enable_reg(u32 nodeid, u32 linkn)

17
src/northbridge/amd/pi/00630F01/northbridge.c
View File

@ -44,7 +44,7 @@
#include <arch/acpigen.h>
#include <assert.h>
#define MAX_NODE_NUMS (MAX_NODES * MAX_DIES)
#define MAX_NODE_NUMS MAX_NODES
#if IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)
#error CONFIG_EXT_CONF_SUPPORT == 1 not support anymore!
@ -110,11 +110,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
static struct device *get_node_pci(u32 nodeid, u32 fn)
{
if (((CONFIG_CDB + nodeid) < 32) || (MAX_NODE_NUMS + CONFIG_CDB < 32)) {
return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
} else {
return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn));
}
return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
}
static void get_fx_devs(void)
@ -157,14 +153,7 @@ static void f1_write_config32(unsigned reg, u32 value)
static u32 amdfam15_nodeid(struct device *dev)
{
unsigned busn;
busn = dev->bus->secondary;
if ((busn != CONFIG_CBB) && (MAX_NODE_NUMS == 64)) {
return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32;
} else {
return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
}
return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
}
static void set_vga_enable_reg(u32 nodeid, u32 linkn)

21
src/northbridge/amd/pi/00660F01/northbridge.c
View File

@ -43,7 +43,7 @@
#include <arch/acpi.h>
#include <arch/acpigen.h>
#define MAX_NODE_NUMS (MAX_NODES * MAX_DIES)
#define MAX_NODE_NUMS MAX_NODES
#if IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)
#error CONFIG_EXT_CONF_SUPPORT == 1 not support anymore!
@ -109,15 +109,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
static struct device *get_node_pci(u32 nodeid, u32 fn)
{
#if MAX_NODE_NUMS + CONFIG_CDB >= 32
if ((CONFIG_CDB + nodeid) < 32) {
return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
} else {
return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn));
}
#else
return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
#endif
}
static void get_fx_devs(void)
@ -160,18 +152,7 @@ static void f1_write_config32(unsigned reg, u32 value)
static u32 amdfam15_nodeid(struct device *dev)
{
#if MAX_NODE_NUMS == 64
unsigned busn;
busn = dev->bus->secondary;
if (busn != CONFIG_CBB) {
return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32;
} else {
return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
}
#else
return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
#endif
}
static void set_vga_enable_reg(u32 nodeid, u32 linkn)

21
src/northbridge/amd/pi/00730F01/northbridge.c
View File

@ -43,7 +43,7 @@
#include <arch/acpi.h>
#include <arch/acpigen.h>
#define MAX_NODE_NUMS (MAX_NODES * MAX_DIES)
#define MAX_NODE_NUMS MAX_NODES
typedef struct dram_base_mask {
u32 base; //[47:27] at [28:8]
@ -105,15 +105,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
static struct device *get_node_pci(u32 nodeid, u32 fn)
{
#if MAX_NODE_NUMS + CONFIG_CDB >= 32
if ((CONFIG_CDB + nodeid) < 32) {
return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
} else {
return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn));
}
#else
return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
#endif
}
static void get_fx_devs(void)
@ -156,18 +148,7 @@ static void f1_write_config32(unsigned reg, u32 value)
static u32 amdfam16_nodeid(struct device *dev)
{
#if MAX_NODE_NUMS == 64
unsigned busn;
busn = dev->bus->secondary;
if (busn != CONFIG_CBB) {
return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32;
} else {
return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
}
#else
return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
#endif
}
static void set_vga_enable_reg(u32 nodeid, u32 linkn)