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nb/intel/sandybridge: Increase tRWDRDD with fast RAM 

This has been reported to increase stability, and vendor BIOS also does
the same.

Change-Id: I4e3ea76f61771683dea61b18bee531516cda5843
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons 2020-11-19 11:04:28 +01:00 committed by Patrick Georgi
parent 08f749d5f6
commit 1146332b9c
1 changed files with 4 additions and 1 deletions
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5
src/northbridge/intel/sandybridge/raminit_common.c
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@ -2778,6 +2778,9 @@ void prepare_training(ramctr_timing *ctrl)
void set_read_write_timings(ramctr_timing *ctrl) void set_read_write_timings(ramctr_timing *ctrl)
{ {
/* Use a larger delay when running fast to improve stability */
const u32 tRWDRDD_inc = ctrl->tCK <= TCK_1066MHZ ? 4 : 2;
int channel, slotrank; int channel, slotrank;
FOR_ALL_POPULATED_CHANNELS { FOR_ALL_POPULATED_CHANNELS {
@ -2800,7 +2803,7 @@ void set_read_write_timings(ramctr_timing *ctrl)
.tRRDD = val, .tRRDD = val,
.tWWDR = val, .tWWDR = val,
.tWWDD = val, .tWWDD = val,
.tRWDRDD = ctrl->ref_card_offset[channel] + 2, .tRWDRDD = ctrl->ref_card_offset[channel] + tRWDRDD_inc,
.tWRDRDD = tWRDRDD, .tWRDRDD = tWRDRDD,
.tRWSR = 2, .tRWSR = 2,
.dec_wrd = 1, .dec_wrd = 1,