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intel/fsp_rangeley: Indent '#define' consistently 

The indentations of #define are not consistent in chip.h. Update to make 
all #define indentations being aligned and put them after the variable 
declaration.

Change-Id: I37550acac18bac3efddb580ef6b956be0e2b357a
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: http://review.coreboot.org/8333
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
York Yang 2015-02-03 14:14:42 -07:00 committed by Martin Roth
parent 582b2aee0f
commit 114baa0a0a
1 changed files with 13 additions and 12 deletions
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25
src/northbridge/intel/fsp_rangeley/chip.h Normal file → Executable file
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@ -52,21 +52,22 @@ struct northbridge_intel_fsp_rangeley_config {
/* Enable the Rank Margin Tool, needs PrintDebugMessages */ /* Enable the Rank Margin Tool, needs PrintDebugMessages */
uint8_t MrcRmtSupport; uint8_t MrcRmtSupport;
#define BIFURCATION_4_4_4_4 0 /* PCIe port bifurcation control */
#define BIFURCATION_4_4_8 1
#define BIFURCATION_8_4_4 2
#define BIFURCATION_8_8 3
#define BIFURCATION_16 4
uint8_t Bifurcation; uint8_t Bifurcation;
#define BIFURCATION_4_4_4_4 0
#define BIFURCATION_4_4_8 1
#define BIFURCATION_8_4_4 2
#define BIFURCATION_8_8 3
#define BIFURCATION_16 4
/* PCIe port de-emphasis control */ /* PCIe port de-emphasis control */
#define DE_EMPHASIS_DEFAULT 0 uint8_t PcdPcieRootPort1DeEmphasis;
#define DE_EMPHASIS_MINUS_6_0_DB 1 uint8_t PcdPcieRootPort2DeEmphasis;
#define DE_EMPHASIS_MINUS_3_5_DB 2 uint8_t PcdPcieRootPort3DeEmphasis;
uint8_t PcdPcieRootPort1DeEmphasis; uint8_t PcdPcieRootPort4DeEmphasis;
uint8_t PcdPcieRootPort2DeEmphasis; #define DE_EMPHASIS_DEFAULT 0
uint8_t PcdPcieRootPort3DeEmphasis; #define DE_EMPHASIS_MINUS_6_0_DB 1
uint8_t PcdPcieRootPort4DeEmphasis; #define DE_EMPHASIS_MINUS_3_5_DB 2
}; };
#endif #endif