mainboard/google/reef: provide baseboard and variant concepts

To further the ability of multiple variant boards to share code
provide a place to land the split up changes. This patch provides
the tooling using a new Kconfig value, VARIANT_DIR, as well as
the Make plumbing. The directory layout with a single variant,
reef (which is also the baseboard), looks like this:

variants/baseboard - code
variants/baseboard/include/baseboard - headers
variants/reef - code
variants/reef/include/variant - headers

New boards would then add themselves under their board name
within the 'variants' directory.

No split has been done with providing different logic yet.
This is purely a organizational change.

BUG=chrome-os-partner:56677

Change-Id: Ib73a3c8a3729546257623171ef6d8fa7a9f16514
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16418
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

src/mainboard/google/reef/Kconfig

@@ -32,6 +32,10 @@ config MAINBOARD_DIR
 	string
 	default google/reef
 
+config VARIANT_DIR
+	string
+	default "reef" if BOARD_GOOGLE_REEF
+
 config MAINBOARD_PART_NUMBER
 	string
 	default "Reef" if BOARD_GOOGLE_REEF

src/mainboard/google/reef/Makefile.inc

@@ -11,3 +11,10 @@ ramstage-y += mainboard.c
 
 verstage-$(CONFIG_CHROMEOS) += chromeos.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+
+subdirs-y += variants/baseboard
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
+
+VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR))
+subdirs-y += variants/$(VARIANT_DIR)
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include

src/mainboard/google/reef/acpi/mainboard.asl

@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#include "../ec.h"
-#include "../gpio.h"
+#include <variant/ec.h>
+#include <variant/gpio.h>
 
 Scope (\_SB)
 {

src/mainboard/google/reef/bootblock.c

@@ -16,8 +16,8 @@
 #include <bootblock_common.h>
 #include <soc/lpc.h>
 #include <soc/gpio.h>
-#include "ec.h"
-#include "gpio.h"
+#include <variant/ec.h>
+#include <variant/gpio.h>
 
 void bootblock_mainboard_init(void)
 {

src/mainboard/google/reef/chromeos.c

@@ -18,8 +18,8 @@
 #include <gpio.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <soc/gpio.h>
-#include "ec.h"
-#include "gpio.h"
+#include <variant/ec.h>
+#include <variant/gpio.h>
 
 #define GPIO_PCH_WP GPIO_75
 #define GPIO_EC_IN_RW GPIO_41

src/mainboard/google/reef/ec.c

@@ -18,7 +18,7 @@
 #include <ec/google/chromeec/ec.h>
 #include <rules.h>
 #include <soc/lpc.h>
-#include "ec.h"
+#include <variant/ec.h>
 
 static void ramstage_ec_init(void)
 {

src/mainboard/google/reef/mainboard.c

@@ -21,8 +21,8 @@
 #include <soc/gpio.h>
 #include <soc/nhlt.h>
 #include <vendorcode/google/chromeos/chromeos.h>
-#include "ec.h"
-#include "gpio.h"
+#include <variant/ec.h>
+#include <variant/gpio.h>
 
 static void mainboard_init(void *chip_info)
 {

src/mainboard/google/reef/romstage.c

@@ -16,7 +16,7 @@
 #include <gpio.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
-#include "gpio.h"
+#include <variant/gpio.h>
 
 static const struct lpddr4_swizzle_cfg board_swizzle = {
 	/* CH0_DQA[0:31] SoC pins -> U22 LPDDR4 module pins */

src/mainboard/google/reef/smihandler.c

@@ -20,8 +20,8 @@
 #include <soc/pm.h>
 #include <soc/smm.h>
 #include <soc/gpio.h>
-#include "ec.h"
-#include "gpio.h"
+#include <variant/ec.h>
+#include <variant/gpio.h>
 
 void mainboard_smi_gpi_handler(const struct gpi_status *sts)
 {

src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h

@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef MAINBOARD_EC_H
-#define MAINBOARD_EC_H
+#ifndef BASEBOARD_EC_H
+#define BASEBOARD_EC_H
 
 #include <ec/google/chromeec/ec_commands.h>
 

src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h

@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef MAINBOARD_GPIO_H
-#define MAINBOARD_GPIO_H
+#ifndef BASEBOARD_GPIO_H
+#define BASEBOARD_GPIO_H
 
 #include <soc/gpio.h>
 
@@ -370,4 +370,4 @@ static const struct pad_config sleep_gpio_table[] = {
 #define MEM_CONFIG0 GPIO_101
 
 #endif /* __ACPI__ */
-#endif /* MAINBOARD_GPIO_H */
+#endif /* BASEBOARD_GPIO_H */

src/mainboard/google/reef/variants/reef/include/variant/ec.h

@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <baseboard/ec.h>
+
+#endif

src/mainboard/google/reef/variants/reef/include/variant/gpio.h

@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif /* MAINBOARD_GPIO_H */