soc/intel/cnl: Enable VT-d
Enable VT-d through fsp upd VtdDisable. Update remapping structure types in numerical order as all remapping structures of type 0 (DRHD) enumerated before remapping structures of type 1 (RMRR), and so forth. BUG=b:130351429 TEST=Booted to kernel and verified the DMAR table contents. Change-Id: I1d20932e417b9d324edd98c8f2195dc228d2e092 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
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@ -304,13 +304,6 @@ static unsigned long soc_fill_dmar(unsigned long current)
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current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
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acpi_dmar_drhd_fixup(tmp, current);
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/* Add RMRR entry */
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tmp = current;
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current += acpi_create_dmar_rmrr(current, 0,
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sa_get_gsm_base(), sa_get_tolud_base() - 1);
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current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
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acpi_dmar_rmrr_fixup(tmp, current);
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}
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struct device *const ipu_dev = dev_find_slot(0, SA_DEVFN_IPU);
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@ -344,6 +337,13 @@ static unsigned long soc_fill_dmar(unsigned long current)
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acpi_dmar_drhd_fixup(tmp, current);
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}
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/* Add RMRR entry */
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const unsigned long tmp = current;
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current += acpi_create_dmar_rmrr(current, 0,
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sa_get_gsm_base(), sa_get_tolud_base() - 1);
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current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
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acpi_dmar_rmrr_fixup(tmp, current);
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return current;
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}
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@ -361,6 +361,7 @@ unsigned long sa_write_acpi_tables(struct device *dev, unsigned long current,
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printk(BIOS_DEBUG, "ACPI: * DMAR\n");
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acpi_create_dmar(dmar, DMAR_INTR_REMAP, soc_fill_dmar);
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current += dmar->header.length;
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current = acpi_align_current(current);
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acpi_add_table(rsdp, dmar);
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@ -344,9 +344,6 @@ struct soc_intel_cannonlake_config {
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/* Enable Pch iSCLK */
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uint8_t pch_isclk;
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/* Intel VT configuration */
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uint8_t VtdDisable;
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/*
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* Acoustic Noise Mitigation
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* 0b - Disable
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@ -101,6 +101,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
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assert(dev != NULL);
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const config_t *config = dev->chip_info;
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FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
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FSP_M_TEST_CONFIG *tconfig = &mupd->FspmTestConfig;
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soc_memory_init_params(m_cfg, config);
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@ -113,6 +114,10 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
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/* Set debug probe type */
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m_cfg->PlatformDebugConsent =
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CONFIG_SOC_INTEL_CANNONLAKE_DEBUG_CONSENT;
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/* Configure VT-d */
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tconfig->VtdDisable = 0;
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mainboard_memory_init_params(mupd);
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}
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@ -33,8 +33,6 @@
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*/
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void soc_add_fixed_mmio_resources(struct device *dev, int *index)
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{
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const struct soc_intel_cannonlake_config *const config = dev->chip_info;
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static const struct sa_mmio_descriptor soc_fixed_resources[] = {
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{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH,
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"PCIEXBAR" },
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@ -63,10 +61,8 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index)
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if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE))
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return;
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if (!(config && config->VtdDisable)) {
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sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources,
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sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources,
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ARRAY_SIZE(soc_vtd_resources));
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}
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}
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/*
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